Cadence Design Systems

1 month ago

Intern: Application Engineering - Digital Verification & Simulation/VIP

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Internship in Digital Verification & Simulation within the System Verification Group (TFO-SVG) in Belo Horizonte. You’ll be trained to support RTL verification products, work with Cadence Verification IP tools, and collaborate with R&D to diagnose issues, develop test cases, and deliver R&D fixes while learning TCL/Python scripting and RTL concepts.

Location: Belo Horizonte

Workplace: Onsite

Employment Type: Part time

Job Function: Healthcare (Clinical, Medical, Wellness)

Seniority: Intern level

Key Responsibilities

•Provide technical support to customers and field personnel in RTL verification solutions focused on Cadence Verification IP solutions and supporting technologies.
•Conduct root cause analysis and provide resolution to customer technical issues.
•Help to develop and run test cases to verify problems, create workarounds when possible, test and deliver R&D fixes.
•Close collaboration with R&D on issues using established protocols.
•Author application notes and help provide feedback on documentation.

Key Requirements

•Ongoing bachelor’s in Electrical Engineering, Computer Engineering, Electronics Engineering, Control and Automation Engineering, Systems Engineering, Computer Science, Information Systems, Computational Mathematics, or related areas; graduating mid-2027.
•Good problem-solving skills.
•Strong interpersonal and communication skills.
•A strong interest in learning the technical topics mentioned above.
•Nice to have: exposure to RTL (Verilog/VHDL) and experience with TCL/Python scripting.

Experience:SemiconductorHardwareDigital verification

Education:Bachelor's in Electrical Engineering

Skills:CommunicationProblem-solvingTeamwork

Tech Stack:XceliumPalladiumProtiumJasperVIPPerspecTCLPython

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

1 month ago

Intern: Application Engineering - Digital Verification & Simulation/VIP

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Belo Horizonte

Workplace: Onsite

Employment Type: Part time

Job Function: Healthcare (Clinical, Medical, Wellness)

Seniority: Intern level

Key Responsibilities

•Provide technical support to customers and field personnel in RTL verification solutions focused on Cadence Verification IP solutions and supporting technologies.
•Conduct root cause analysis and provide resolution to customer technical issues.
•Help to develop and run test cases to verify problems, create workarounds when possible, test and deliver R&D fixes.
•Close collaboration with R&D on issues using established protocols.
•Author application notes and help provide feedback on documentation.

Key Requirements

•Ongoing bachelor’s in Electrical Engineering, Computer Engineering, Electronics Engineering, Control and Automation Engineering, Systems Engineering, Computer Science, Information Systems, Computational Mathematics, or related areas; graduating mid-2027.
•Good problem-solving skills.
•Strong interpersonal and communication skills.
•A strong interest in learning the technical topics mentioned above.
•Nice to have: exposure to RTL (Verilog/VHDL) and experience with TCL/Python scripting.

Experience:SemiconductorHardwareDigital verification

Education:Bachelor's in Electrical Engineering

Skills:CommunicationProblem-solvingTeamwork

Tech Stack:XceliumPalladiumProtiumJasperVIPPerspecTCLPython

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor