DV Intern
San Jose
Workplace: OnsiteFull timeFunction: Healthcare (Clinical, Medical, Wellness)Skills: ["SystemVerilog","UVM","Python"]Design Verification intern to verify custom IPs powering Etched chips (systolic arrays, DMA engines, NoCs) ensuring robustness, high performance, and silicon-readiness, collaborating with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
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