Leadership Role - DFT

AMD
Bengaluru
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 14+ yearsSkills: ["Technical leadership","Cross-functional collaboration","Debugging","Mentoring","Technical influence"]

Lead end-to-end ATPG strategy, implementation, and pattern validation for complex, multi-million gate SoCs. Drive ATPG execution from DFT architecture definition through pre-silicon verification, production test enablement, silicon bring-up, and manufacturing ramp. Partner with RTL/DFT RTL, DFT verification, physical design, PEO, ATE, and silicon validation teams to deliver high-quality, cost-effective test content, ensure coverage closure and signoff, and resolve ATPG/test/silicon yield issues while mentoring engineers and improving automation.

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FursaFursa
AMD
AMD
1 month ago

Leadership Role - DFT

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Lead end-to-end ATPG strategy, implementation, and pattern validation for complex, multi-million gate SoCs. Drive ATPG execution from DFT architecture definition through pre-silicon verification, production test enablement, silicon bring-up, and manufacturing ramp. Partner with RTL/DFT RTL, DFT verification, physical design, PEO, ATE, and silicon validation teams to deliver high-quality, cost-effective test content, ensure coverage closure and signoff, and resolve ATPG/test/silicon yield issues while mentoring engineers and improving automation.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Sr. Manager level

Key Responsibilities

  • •Own end-to-end ATPG execution for large-scale SoCs from architecture phase through silicon production.
  • •Define and drive ATPG methodologies, test strategies, coverage closure plans, and pattern signoff criteria.
  • •Generate and validate scan, transition fault, cell-aware, bridge, chain diagnosis, and compression-based ATPG patterns.
  • •Lead pattern validation across simulation, emulation, ATE, and platform environments; drive tester correlation and debug.
  • •Develop automation flows and AI-enabled solutions, perform root-cause analysis for ATPG/test/silicon/yield issues, and mentor junior engineers.

Key Requirements

  • •14+ years of experience in SoC DFT with strong expertise in ATPG and manufacturing test.
  • •Proven ownership of ATPG execution for multiple successful high-volume SoC products.
  • •Deep understanding of Scan, EDT/Compression, LBIST, MBIST, Boundary Scan, and DFT architecture.
  • •Strong experience with scan/pattern validation, tester correlation, and post-silicon debug.
  • •Strong scripting and automation skills using Python, Perl, Tcl, Shell, or similar languages.
Experience:14+ yearsSemiconductorSoC DFTManufacturing test
Education:
Skills:Technical leadershipCross-functional collaborationDebuggingMentoringTechnical influence
Tech Stack:ATPGScanDFTTessentModusTestMAXTetraMAXSTILWGLEDT/CompressionLBISTMBISTBoundary ScanPythonPerlTclShellAI-enabled solutionsSimulationEmulation

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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