Leadership Role - DFT

Lead end-to-end ATPG strategy, implementation, and pattern validation for complex, multi-million gate SoCs. Drive ATPG execution from DFT architecture definition through pre-silicon verification, production test enablement, silicon bring-up, and manufacturing ramp. Partner with RTL/DFT RTL, DFT verification, physical design, PEO, ATE, and silicon validation teams to deliver high-quality, cost-effective test content, ensure coverage closure and signoff, and resolve ATPG/test/silicon yield issues while mentoring engineers and improving automation.