Principal Analog IC Design Engineer, High Speed SerDes

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 136,500 - 253,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsEducation: mastersSkills: ["Problem solving","Communication","Team collaboration","Analog aptitude"]

Design and develop analog/mixed-signal IC circuit blocks from concept through final verification, ensuring conformance to customer specifications for high-speed SerDes and I/O. Own key design areas including jitter-aware signal equalization, PLLs, clock distribution, and serializer/deserializer blocks. Use CAD tools for simulation, layout, and physical verification, collaborating in a team environment and working on designs targeting >10Gbps performance.

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Cadence Design Systems
Cadence Design Systems
2 days ago

Principal Analog IC Design Engineer, High Speed SerDes

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Last checked: 12 hours agoStatus: Live

Job Summary

Design and develop analog/mixed-signal IC circuit blocks from concept through final verification, ensuring conformance to customer specifications for high-speed SerDes and I/O. Own key design areas including jitter-aware signal equalization, PLLs, clock distribution, and serializer/deserializer blocks. Use CAD tools for simulation, layout, and physical verification, collaborating in a team environment and working on designs targeting >10Gbps performance.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Design and develop analog/mixed-signal IC circuit blocks from initial concept/specification through final verification.
  • •Ensure designed circuitry conforms to customer specifications.
  • •Apply jitter and signal equalization techniques to high-speed SerDes designs.
  • •Develop key SerDes blocks including driver/receiver, serializer/deserializer, and PLL-based components.
  • •Use CAD tools for circuit simulation, layout, and physical verification while collaborating with the team.

Pay and Benefits

Salary: USD 136,500 - 253,500 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid Holidays401kEquityHealth InsuranceDentalVision

Key Requirements

  • •Minimum 7 years of experience in CMOS SerDes or high-speed I/O IC design and development.
  • •Thorough understanding of jitter and signal equalization techniques.
  • •Proficient design experience across SerDes circuit blocks (e.g., driver/receiver/serializer/deserializer, PLL, clock distribution).
  • •Proficiency using CAD tools for circuit simulation, layout, and physical verification.
  • •MS or PhD in EE, plus experience with Cadence tools and lab testing at >10Gbps (mentioned as requirements/background).
Experience:7+ years
Education:Master's in EE
Skills:Problem solvingCommunicationTeam collaborationAnalog aptitude
Tech Stack:Analog/mixed signal ICCMOSSerDesHigh-speed I/OJitterSignal equalizationDriverReceiverSerializerDeserializerPhase InterpolatorLow jitter PLLHigh Speed Clock DistributionADCDACBiasBandgapVoltage RegulatorsCAD toolsCircuit simulation

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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