Advanced Packaging Photolithography Development Engineer

Intel
United States
Workplace: OnsiteFull timeUSD 133,800 - 188,890 annuallyFunction: Product ManagementExperience: 2+ yearsEducation: mastersSkills: ["Analytical and problem-solving","Root cause analysis","Systematic defect analysis"]

Drive photolithography process development for next-generation semiconductor packaging, including hybrid bonding applications. Qualify scanner/stepper platforms, develop and optimize back-end patterning processes (e.g., Cu damascene, dielectric vias/trenches, bonding interface layers), and implement overlay metrology and advanced process control with run-to-run feedback. Collaborate cross-functionally across integration, equipment, metrology, and design teams to improve yield through defect analysis and corrective actions while supporting technology roadmap planning.

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Intel
Intel
1 day ago

Advanced Packaging Photolithography Development Engineer

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Job Summary

Drive photolithography process development for next-generation semiconductor packaging, including hybrid bonding applications. Qualify scanner/stepper platforms, develop and optimize back-end patterning processes (e.g., Cu damascene, dielectric vias/trenches, bonding interface layers), and implement overlay metrology and advanced process control with run-to-run feedback. Collaborate cross-functionally across integration, equipment, metrology, and design teams to improve yield through defect analysis and corrective actions while supporting technology roadmap planning.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Product Management
Seniority: Mid level

Key Responsibilities

  • •Qualify scanner/stepper platforms and track systems for backend and hybrid bonding lithography applications.
  • •Develop, characterize, and optimize photolithography processes for back-end applications, including Cu damascene pad patterning, dielectric via/trench lithography, bonding interface layer patterning, and alignment/overlay targets.
  • •Evaluate and implement underlayer stacks to address topography challenges in far backend and packaging substrates.
  • •Develop and optimize overlay metrology and control strategies, including APC with run-to-run and lot-to-lot overlay feedback/feedforward loops.
  • •Support yield learning via defect analysis, root cause investigation, and corrective actions; collaborate to deliver fully integrated process flows and engage in roadmap planning with equipment/material suppliers.

Pay and Benefits

Salary: USD 133,800 - 188,890 annually
Perks:Health InsuranceRetirementPaid LeaveEquity

Key Requirements

  • •Master’s degree in Materials Science and Engineering, Mechanical Engineering, Chemical Engineering, Electrical Engineering, Physics, Chemistry, or related fields with 3+ years of relevant experience, or a PhD in the same fields with 2+ years of relevant experience.
  • •Hands-on lithography process development experience with i-line, KrF, or ArF in a semiconductor fab.
  • •Hands-on photoresist process development (coat/bake/develop optimization, resist profile engineering, and process window characterization).
  • •Strong understanding of optical lithography fundamentals (aerial image formation, FEM, DOF, exposure latitude).
  • •Proficiency in Statistical Process Control (SPC) and Design of Experiments (DOE) principles; preferred experience with packaging lithography environments and overlay metrology/control (e.g., CDSEM, OCD/scatterometry).
Experience:2+ yearsSemiconductorsSemiconductor fabricationAdvanced packagingLithographyHybrid bonding
Education:Master's
Skills:Analytical and problem-solvingRoot cause analysisSystematic defect analysis
Tech Stack:I-lineKrFArF lithographyPhotolithographyPhotoresistCoat/bake/developSPCDOEFEMDOFExposure latitudeAPCRun-to-run (R2R)Overlay metrologyCDSEMOCD/scatterometryFoverosFoveros DirectFan-out WLP2.5D/3D IC

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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