IP Design Verification Engineer
Intel
Phoenix, Santa Clara
Workplace: OnsiteFull timeUSD 141,910 - 200,340 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 4+ yearsEducation: bachelorsSkills: ["SystemVerilog","Verilog","UVM","OVM","ECAD","VCS","Xcelium","JasperGold","Questa","Analog modeling","Power analysis"]Join Intel as a Mixed Signal Design Verification Engineer to verify Intel’s mixed-signal IPs, develop verification plans, and build test benches using UVM/OVM. You’ll model analog behavior, debug presilicon issues, analyze coverage, and collaborate across disciplines to ensure designs meet power, timing, and performance targets for world-class semiconductor solutions.
