SENIOR ASIC Engineer

Micron Technology
Taiwan
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 7+ yearsEducation: mastersSkills: ["Problem-solving","Process improvement","Self-motivated","Self-directed","Team collaboration","Technical communication","Relationship building"]

Lead SoC integration and RTL integration across CPU subsystems, interconnects, peripheral IPs, clock/power/reset, and test structures. Own SoC RTL integration checks (lint/CDC/RC), synthesis constraints, and timing closure support, while defining SoC-level interfaces and integration specifications. Integrate and validate CPU cores/clusters and optimize performance, power, and area boundaries. Collaborate with DFT, physical design, verification, firmware, and validation teams to bring up test modes, support pre/post-silicon validation, and drive root-cause analysis for silicon debug.

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FursaFursa
Micron Technology
Micron Technology
5 months ago

SENIOR ASIC Engineer

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Last checked: 6 hours agoStatus: Live

Job Summary

Lead SoC integration and RTL integration across CPU subsystems, interconnects, peripheral IPs, clock/power/reset, and test structures. Own SoC RTL integration checks (lint/CDC/RC), synthesis constraints, and timing closure support, while defining SoC-level interfaces and integration specifications. Integrate and validate CPU cores/clusters and optimize performance, power, and area boundaries. Collaborate with DFT, physical design, verification, firmware, and validation teams to bring up test modes, support pre/post-silicon validation, and drive root-cause analysis for silicon debug.
Location: Taiwan
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Lead top-level SoC integration (CPU subsystem, interconnect, peripheral IPs, clock/power/reset, and test structures) and support RTL integration and timing closure.
  • •Own SoC RTL integration checks (lint/CDC/RC), synthesis constraints, and define SoC-level interfaces, connectivity, and integration specifications.
  • •Integrate and validate CPU cores/clusters and optimize performance, power, and area (PPA) across CPU and SoC boundaries.
  • •Collaborate with DFT to integrate scan, MBIST, LBIST, boundary scan, and other SoC-level test structures; ensure testability requirements and coverage goals.
  • •Support pre-silicon simulation/emulation and post-silicon bring-up, including test mode bring-up and root-cause analysis/resolution during silicon debug.

Key Requirements

  • •MS in Electrical Engineering with 13+ years of experience (SoC qualifications).
  • •Own SoC RTL integration, including lint/CDC/RC checking, synthesis constraints, and timing closure support.
  • •Define and maintain SoC-level interfaces and integration specifications, partnering with architecture and design teams.
  • •Integrate and validate CPU cores or CPU clusters (ARM, ARC, RISC‑V, or proprietary designs) and optimize PPA at CPU/SoC boundaries.
  • •MS in Electrical Engineering with 7–10 years of design experience required for IP qualifications; proficient in Verilog/SystemVerilog RTL or testbench development and complex logic integration/validation.
Experience:7+ years
Education:Master's in Electrical Engineering
Skills:Problem-solvingProcess improvementSelf-motivatedSelf-directedTeam collaborationTechnical communicationRelationship building
Languages:English
Tech Stack:SoCRTLVerilogSystemVerilogVCSVC-SpyglassCDCLINTRDCLECDesign CompilerFormalityPrimeTimeTCLPERLPythonCPU subsystemInterconnectClock/power/resetCPU cores

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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