Layout Engineering Intern m/f/d

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Work on mixed-signal integrated circuit layout within a cross-functional design team. You’ll contribute to block-level IC layout, top-level integration, floor planning, and area estimation for next-generation DC/DC converter and power stage solutions. Responsibilities include physical verification and post-layout analysis (DRC/LVS/EM/ESD), designing transistor and lead frame layouts, and helping automate layout design flow and verification using advanced tools.

Location: Germany

Workplace: Onsite

Employment Type: Internship

Job Function: Healthcare (Clinical, Medical, Wellness)

Seniority: Intern level

Key Responsibilities

•Create block-level IC layouts, perform top-level integration, and support floor planning and area estimation.
•Design power transistor and package lead frame layouts for discrete and module devices.
•Conduct die and package-board parasitic extraction and support physical verification and post-layout analysis (DRC, LVS, EM, ESD).
•Use advanced tools to automate basic block-level layout tasks, floor planning, and area estimations.
•Collaborate with analog/digital design and other cross-functional teams; participate in layout design reviews and support design flow automation/verification development.

Key Requirements

•Be in your final years of ongoing studies (bachelor or master) in Electrical Engineering or an equivalent field.
•Submit your latest grades transcript with your application.
•Good understanding of analog electronics theory and device physics.
•Experience with Cadence Virtuoso or equivalent IC layout design tools.
•Ability to work in teams and collaborate effectively across different functions.

Education:Bachelor's in Electrical Engineering

Skills:CollaborationInitiativeTime managementCommunicationProblem-solving

Languages:EnglishGerman

Tech Stack:Cadence VirtuosoCadence databaseUnixDRCLVSEMESDFloor planning

Company Brief

Texas Instruments

Industry: Electronics Manufacturing

Website

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Texas Instruments

1 month ago

Layout Engineering Intern m/f/d

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Location: Germany

Workplace: Onsite

Employment Type: Internship

Job Function: Healthcare (Clinical, Medical, Wellness)

Seniority: Intern level

Key Responsibilities

•Create block-level IC layouts, perform top-level integration, and support floor planning and area estimation.
•Design power transistor and package lead frame layouts for discrete and module devices.
•Conduct die and package-board parasitic extraction and support physical verification and post-layout analysis (DRC, LVS, EM, ESD).
•Use advanced tools to automate basic block-level layout tasks, floor planning, and area estimations.
•Collaborate with analog/digital design and other cross-functional teams; participate in layout design reviews and support design flow automation/verification development.

Key Requirements

•Be in your final years of ongoing studies (bachelor or master) in Electrical Engineering or an equivalent field.
•Submit your latest grades transcript with your application.
•Good understanding of analog electronics theory and device physics.
•Experience with Cadence Virtuoso or equivalent IC layout design tools.
•Ability to work in teams and collaborate effectively across different functions.

Education:Bachelor's in Electrical Engineering

Skills:CollaborationInitiativeTime managementCommunicationProblem-solving

Languages:EnglishGerman

Tech Stack:Cadence VirtuosoCadence databaseUnixDRCLVSEMESDFloor planning

Company Brief

Texas Instruments

Industry: Electronics Manufacturing

Website