Design Verification Engineering Intern - MS/PhD
Dallas, Phoenix
Workplace: OnsiteInternshipFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Communication","Interpersonal skills","Analytical skills","Problem-solving","Team collaboration"]As a Design Verification intern, you’ll partner with design and system teams to create detailed verification plans and ensure pre-silicon success. Build test benches, simulations, and constrained-random analog stimulus environments, then run coverage regressions using SystemVerilog functional coverage models. You’ll track and communicate verification status, develop regression scripts, and verify RTL and Gates+SDF timing across analog and digital circuits while improving DV quality and efficiency.
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