3 months ago

Sr Principal Product Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 2 hours agoStatus: Live

Job Summary

Lead and drive customer engagements to solve verification challenges using leading edge Cadence verification technologies (e.g., vManager). Collaborate with key customers to deploy advanced verification and debug solutions, review customer requirements with development teams, and educate field on new solutions. Develop strategy roadmaps for Smart Verification flows, write and review specifications, and ensure customer success across global deployments.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Seniority: Sr. Manager level

Key Responsibilities

•Understand customer challenges and drive requirements to the development teams, understanding priority, value, and timeliness of the ultimate solution.
•Support the development of key verification flows and methodologies to improve the Smart Verification Solutions at Cadence focusing on the unique requirements of the design and verification community.
•Help develop strategy and technology roadmaps for product engineering Smart Verification flows and related applications that drive the value of the full Cadence verification suite.
•Write requirement specifications and review functional specifications to ensure relevant solutions are provided to customers.
•Lead and drive customer engagement to solve verification challenges with leading edge technologies and methodologies such as vManager, coordinating with development groups

Travel: High travel

Key Requirements

•Degree in Electrical or Computer Engineering, graduate level or compensating experience
•At least 12+ years hands-on experience with verification
•Knowledgeable on EDA tools and verification solution (Cadence or others)
•Expertise in Functional Verification flows e.g. coverage driven verification, constrained random testing, etc.
•Knowledgeable on design and verification languages and methodologies like SystemVerilog, VHDL, C/C++ UVM, ‘e’

Experience:12+ yearsEDAVerificationFunctional verificationCadenceVmanager

Education:Master's

Skills:Verbal communicationWritten communicationTeamwork

Languages:English

Tech Stack:SystemVerilogVHDLC/C++UVMEVManager

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

3 months ago

Sr Principal Product Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 2 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Seniority: Sr. Manager level

Key Responsibilities

•Understand customer challenges and drive requirements to the development teams, understanding priority, value, and timeliness of the ultimate solution.
•Support the development of key verification flows and methodologies to improve the Smart Verification Solutions at Cadence focusing on the unique requirements of the design and verification community.
•Help develop strategy and technology roadmaps for product engineering Smart Verification flows and related applications that drive the value of the full Cadence verification suite.
•Write requirement specifications and review functional specifications to ensure relevant solutions are provided to customers.
•Lead and drive customer engagement to solve verification challenges with leading edge technologies and methodologies such as vManager, coordinating with development groups

Travel: High travel

Key Requirements

•Degree in Electrical or Computer Engineering, graduate level or compensating experience
•At least 12+ years hands-on experience with verification
•Knowledgeable on EDA tools and verification solution (Cadence or others)
•Expertise in Functional Verification flows e.g. coverage driven verification, constrained random testing, etc.
•Knowledgeable on design and verification languages and methodologies like SystemVerilog, VHDL, C/C++ UVM, ‘e’

Experience:12+ yearsEDAVerificationFunctional verificationCadenceVmanager

Education:Master's

Skills:Verbal communicationWritten communicationTeamwork

Languages:English

Tech Stack:SystemVerilogVHDLC/C++UVMEVManager

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor