Digital Design RTL Engineer

Broadcom
Colorado, United States
Workplace: OnsiteFull timeUSD 121,900 - 195,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Autonomy","Cross-functional collaboration","Risk mitigation","Timing closure","Physical design hand-off"]

Deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below), taking designs from initial specification through timing closure and physical-design handoff. Optimize performance and power (PPA), analyze clock domain crossing (CDC) and reset domain crossing (RDC), and apply low-power design techniques. Work cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and meet project milestones on schedule.

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FursaFursa
Broadcom
Broadcom
1 month ago

Digital Design RTL Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 11 days agoStatus: Live

Job Summary

Deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below), taking designs from initial specification through timing closure and physical-design handoff. Optimize performance and power (PPA), analyze clock domain crossing (CDC) and reset domain crossing (RDC), and apply low-power design techniques. Work cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and meet project milestones on schedule.
Location: Colorado, United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Take RTL designs from initial specification through timing closure and physical design hand-off with high autonomy.
  • •Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks.
  • •Analyze and address clock domain crossing (CDC) and reset domain crossing (RDC) issues.
  • •Drive performance and power (PPA) optimization for advanced process node designs.
  • •Implement low-power design techniques alongside RTL development and project execution.

Pay and Benefits

Salary: USD 121,900 - 195,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEsppPaid HolidaysPaid LeaveParental Leave

Key Requirements

  • •BSEE required; MSEE/PHD preferred.
  • •High proficiency delivering SystemVerilog RTL in advanced process nodes (5nm and below).
  • •Deep understanding of RTL design, including PPA optimization and clock domain crossing (CDC) and reset domain crossing (RDC).
  • •Experience with low-power design techniques.
  • •8+ years of industry experience with SoC integration and interfaces including LPDDR5/6, DDR4/5, high-speed SerDes, and/or HBM protocols highly preferred.
Experience:8+ yearsSoC integration
Education:Bachelor's
Skills:AutonomyCross-functional collaborationRisk mitigationTiming closurePhysical design hand-off
Tech Stack:SystemVerilogRTL designPPA optimizationCDC analysisRDCLow-power designSoC integrationLPDDR5LPDDR6DDR4DDR5High-speed SerDesHBM protocols

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn