Sr. RTL Design Engineer

AMD
San Jose
Workplace: HybridFull timeUSD 175,000 - 300,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Problem-solving","Analytical thinking","Collaboration","Communication","Adaptability"]

Design and implement RTL for complex digital and mixed-signal blocks for FPGA product and platform development. Own the RTL-to-GDS design flow including synthesis, DFT, place-and-route, and Static Timing Analysis. Partner with functional verification teams using SystemVerilog and UVM, and use scripting (Perl, Tcl, Shell, Python) to maintain and build design automation tools. Collaborate across global engineering teams to drive milestones and technical execution.

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FursaFursa
AMD
AMD
1 day ago

Sr. RTL Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 40 minutes agoStatus: Live

Job Summary

Design and implement RTL for complex digital and mixed-signal blocks for FPGA product and platform development. Own the RTL-to-GDS design flow including synthesis, DFT, place-and-route, and Static Timing Analysis. Partner with functional verification teams using SystemVerilog and UVM, and use scripting (Perl, Tcl, Shell, Python) to maintain and build design automation tools. Collaborate across global engineering teams to drive milestones and technical execution.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Participate in the RTL development to GDS design flow for FPGA product and platform development programs.
  • •Design and implement RTL for complex digital and mixed-signal blocks using Verilog and SystemVerilog.
  • •Support physical design activities including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
  • •Collaborate with functional verification teams to support block-level verification using SystemVerilog and UVM.
  • •Use scripting (Perl, Tcl, Shell, Python) to maintain and develop design automation flows and tools, and communicate with global project teams to resolve technical issues.

Pay and Benefits

Salary: USD 175,000 - 300,000 annually

Key Requirements

  • •Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
  • •Strong RTL design and integration experience using Verilog and SystemVerilog.
  • •Working knowledge of physical design concepts including synthesis, place-and-route, timing closure, and Static Timing Analysis (STA).
  • •Hands-on experience implementing DFT for large-scale SoCs (e.g., scan, compression, MBIST, LBIST, boundary scan).
  • •Experience with UVM/OVM verification methodologies, testbench development, BFMs, and debug workflows.
Education:Master's in electrical engineering, computer engineering
Skills:Problem-solvingAnalytical thinkingCollaborationCommunicationAdaptability
Tech Stack:FPGARTLVerilogSystem VerilogGDSEDASynthesisDFTPlace-and-routeStatic Timing Analysis (STA)UVMOVMConstrained-randomDirected testsPerlTclShellPythonSynopsys DFT CompilerTestMAX

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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