R&D Engineer IC Design
San Jose
Workplace: OnsiteFull timeUSD 120,000 - 192,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 6+ yearsEducation: mastersSkills: ["SystemVerilog","C","Scripting"]Hardware-focused R&D engineer responsible for verification of complex switch designs in ICs. Create SystemVerilog testbenches and testplans, verify RTL and gatesim at block and chip level, and develop ATE vectors and C-based diagnostic tests for silicon. Strong emphasis on verification methods, UVM knowledge preferred.

