HBM SoC Physical Design Engineer

Micron Technology
Texas
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: bachelorsSkills: ["Collaboration","Problem-solving","Attention to detail","Process improvement","Mentoring"]

Drive SoC physical implementation for advanced HBM SoC designs, taking logic/base die work from netlist to GDSII. Own key stages such as floorplanning, placement, clock tree synthesis, routing, and physical optimization to hit performance, power, and area targets. Lead timing closure across multi-mode/multi-corner scenarios, integrate complex IP, coordinate physical signoff (DRC/LVS/IR drop/timing), and support tape-out and post-silicon debug. Improve flow productivity via scripting/automation.

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FursaFursa
Micron Technology
Micron Technology
2 months ago

HBM SoC Physical Design Engineer

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Last checked: 20 hours agoStatus: Live
Reposted: first listed 17 hours ago

Job Summary

Drive SoC physical implementation for advanced HBM SoC designs, taking logic/base die work from netlist to GDSII. Own key stages such as floorplanning, placement, clock tree synthesis, routing, and physical optimization to hit performance, power, and area targets. Lead timing closure across multi-mode/multi-corner scenarios, integrate complex IP, coordinate physical signoff (DRC/LVS/IR drop/timing), and support tape-out and post-silicon debug. Improve flow productivity via scripting/automation.
Location: Texas
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
  • •Drive timing closure (setup/hold) across multi-mode/multi-corner scenarios in partnership with RTL, architecture, and STA/signoff teams.
  • •Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on physical integration and timing/power integrity.
  • •Perform and/or coordinate physical signoff including DRC/LVS and IR drop/EM and timing signoff, addressing violations efficiently.
  • •Coordinate with DFT, packaging/assembly, test, probe, and manufacturing teams for physically realizable scan/MBIST requirements, tape-out execution, and post-silicon debug correlation.

Pay and Benefits

Perks:Health InsuranceDentalVisionPaid LeavePaid HolidaysParental LeaveIncome Protection

Key Requirements

  • •Strong SoC physical design implementation experience from netlist to GDSII on advanced nodes and complex designs.
  • •Proficiency with EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, and Siemens Calibre or equivalents.
  • •Solid STA fundamentals, clocking, constraints (SDC), and closure techniques like buffering, path shaping, and useful skew.
  • •Experience with power intent and power delivery concepts, including UPF/CPF, power grid planning, and power gating implications.
  • •Familiarity with physical verification/signoff (DRC, LVS, ERC) and parasitic extraction awareness, with quality signoff handoff.
Experience:10+ yearsSemiconductorSoC physical designHBMDRAMAdvanced nodes
Education:Bachelor's in Electrical Engineering or Computer Engineering
Skills:CollaborationProblem-solvingAttention to detailProcess improvementMentoring
Tech Stack:Cadence InnovusCadence TempusSynopsys ICC2Synopsys PrimeTimeSiemens CalibreSTASDCUPFCPFPower grid planningPower gatingDRCLVSERCParasitic extractionGDSIIFloor-planningCTSRoutingTiming signoff

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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