ASIC Physical Design Engineer (RDSS Intern)

Support ASIC physical design activities from RTL frozen through tape out, including chip integration and netlist generation, synthesis, RTL/netlist quality checks, formal verification, and constraints creation/validation for timing closure. Collaborate with ASIC and PR engineers to resolve special timing issues, implement partitioning and floorplanning, and achieve timing closure for partition and full-chip as well as special modes. Build and improve timing-closure flows, automation, and methodology tools.