IP Design Verification Engineer
Penang
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["SystemVerilog","OVM","UVM","Verilog","RTL","DFx","BFM","System Verilog","C","Shell scripting","Python","Perl","Tcl","Tk"]Join Intel as an IP Design Verification Engineer contributing to RTL validation and verification of high‑end IPs for SoC applications. You’ll develop OVM/UVM test benches, define verification strategies, create BFMs, run GLS, and automate pre-silicon validation using Tcl/Python, collaborating with RTL, architecture and physical design teams to ensure robust IP verification for LPDDR5 and DDR5 on leading process nodes.
