NAND Design Rule Manager

Micron Technology
Singapore
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: phdSkills: ["Leadership","Communication","Problem-solving","Stakeholder management"]

Lead a team supporting development and large-scale production of advanced 3D NAND technologies by driving accurate design-rule and PDK results. Release design rules and PDK deliverables, coordinate DRC waivers, mask definitions, and reviews, and own program execution from kickoff to end-of-life. Partner across process integration, layout, modeling, scribe & frame, and quality teams to ensure high-quality build rule checks, resolve deviations, and improve the design-rule pathfinding for next-generation production.

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FursaFursa
Micron Technology
Micron Technology
1 month ago

NAND Design Rule Manager

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Job Summary

Lead a team supporting development and large-scale production of advanced 3D NAND technologies by driving accurate design-rule and PDK results. Release design rules and PDK deliverables, coordinate DRC waivers, mask definitions, and reviews, and own program execution from kickoff to end-of-life. Partner across process integration, layout, modeling, scribe & frame, and quality teams to ensure high-quality build rule checks, resolve deviations, and improve the design-rule pathfinding for next-generation production.
Location: Singapore
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Lead the release of design rules and PDK deliverables, coordinating DRC waivers, mask definitions, and mask reviews for both R&D and production.
  • •Own program execution from kickoff through end-of-life and define sub-milestones within PDK/DBR/TO schedules to meet targets through cross-team coordination.
  • •Partner across Array & CMOS Process Integration, Devices, Layout & Build, Modeling, Scribe & Frame, unit process areas, and Quality & Reliability to guide new 3D NAND generations.
  • •Ensure build rule checks (DRCs) are high quality and drive timely disposition of deviations, exceptions, and corrective actions with Yield Improvement, Product Engineering, Defect Analysis, and Quality Assurance.
  • •Build and evaluate test structures to generate data for next-generation devices, synthesize technical problems, and communicate status, risks, and resolutions clearly while driving continuous improvement.

Key Requirements

  • •PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years of relevant experience, or Master’s with 8+ years, or bachelor’s with 13+ years in the semiconductor industry.
  • •Direct experience working with PDK, design rules, and layout, including small layout assignments.
  • •Skilled in CAD software such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE or equivalents.
  • •Strong understanding of semiconductor device physics and VLSI silicon processing and integration flow.
  • •Knowledge of 3D NAND process flow and major NAND components, plus the ability to resolve complex issues and communicate clearly under pressure.
Experience:Semiconductor industry3D NAND
Education:PhD / Doctorate
Skills:LeadershipCommunicationProblem-solvingStakeholder management
Tech Stack:PDKDesign rulesCadence VirtuosoK2ViewMentor GraphicsDRC/RVECADDRCsMask definitionsReticlesPHOTO/OPC/CMP

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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