ASIC TOP Floorplan Design Engineer

NVIDIA
Shanghai
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: mastersSkills: ["Communication","Interpersonal skills","Teamwork","Collaboration"]

Design and optimize ASIC floorplans during early chip development, partnering with architects, design leads, physical design leads, and package leads. Lead area review, identify area/interconnect/floorplan improvements, and help resolve timing and routing congestion by influencing early implementation decisions. Build and enhance tools and infrastructure using AI to optimize chip area and improve execution speed for next-generation GPUs and SoCs.

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FursaFursa
NVIDIA
NVIDIA
1 day ago

ASIC TOP Floorplan Design Engineer

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Last checked: 8 minutes agoStatus: Live

Job Summary

Design and optimize ASIC floorplans during early chip development, partnering with architects, design leads, physical design leads, and package leads. Lead area review, identify area/interconnect/floorplan improvements, and help resolve timing and routing congestion by influencing early implementation decisions. Build and enhance tools and infrastructure using AI to optimize chip area and improve execution speed for next-generation GPUs and SoCs.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •Develop, craft, and optimize floorplans during early chip development in collaboration with architects and design leads.
  • •Drive the area review process and collaborate to identify area, interconnect, and floorplan improvement opportunities.
  • •Address timing and routing congestion by influencing early design and physical implementation decisions.
  • •Build and improve tools and infrastructure using AI to optimize chip area and speed of execution.

Key Requirements

  • •Master’s degree in electrical engineering, Computer Science, or Computer Engineering and 1+ year equivalent work/learning experience.
  • •Experience in Verilog, System Verilog, or similar HVL.
  • •Experience with CAD and physical design methodologies, including chip floorplan, power/clock distribution, packaging, P&R, and timing closure.
  • •Programming language experience with Python, Perl, and C/C++.
  • •Experience using AI coding assistants like Cursor or GitHub Copilot or Windchill.
Experience:1+ years
Education:Master's
Skills:CommunicationInterpersonal skillsTeamworkCollaboration
Languages:English
Tech Stack:ASIC floorplanVerilogSystemVerilogHVLCADPhysical designPower/clock distributionPackagingP&RTiming closurePythonPerlC/C++CursorGitHub CopilotWindchillAI coding assistants

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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