Senior RTL Design Engineer

AMD
San Jose
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Verilog","SystemVerilog","HDL","RTL design","Timing closure","Microarchitecture","Synthesis","STA","DFT","DFD","Debugging","Signal integrity","Clock domain crossing","AMBA AXI","PCIe","CXL","AMBA"]

Senior ASIC design engineer responsible for the full RTL design lifecycle of complex IP blocks for next-generation embedded products. Own micro-architecture specifications, Verilog RTL implementation, timing closure, and integration into SOCs; collaborate across architecture, verification, physical design, and post-silicon teams; mentor junior engineers and drive production tape-outs while achieving PPA targets.

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FursaFursa
AMD
AMD
5 months ago

Senior RTL Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Senior ASIC design engineer responsible for the full RTL design lifecycle of complex IP blocks for next-generation embedded products. Own micro-architecture specifications, Verilog RTL implementation, timing closure, and integration into SOCs; collaborate across architecture, verification, physical design, and post-silicon teams; mentor junior engineers and drive production tape-outs while achieving PPA targets.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA targets and timing requirements.
  • •Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
  • •Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry-standard tools, resolve timing violations, and collaborate with physical design to achieve timing closure.
  • •SOC Integration: Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity, clock domain crossings, and interface compliance with AMBA AXI/AHB/APB, PCIe, CXL.
  • •Design Quality & Verification: Partner with verification teams to ensure comprehensive functional coverage; implement DFT/DFD features; participate in RTL quality reviews and signoff.
  • •Physical Design Collaboration: Work with physical design engineers on floorplanning, placement constraints, clock tree synthesis, and power grid design to ensure timing convergence.

Key Requirements

  • •2+ production ASIC tape-outs in a senior design role
  • •Expert-level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs
  • •Hands-on experience with the complete ASIC design flow: RTL → Synthesis → STA → Physical Design → Tape-out
  • •Experience writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints
  • •Experience integrating complex IP blocks into SOC designs
Experience:SemiconductorASICEmbedded systemsSilicon design
Education:Bachelor's
Skills:VerilogSystemVerilogHDLRTL designTiming closureMicroarchitectureSynthesisSTADFTDFDDebuggingSignal integrityClock domain crossingAMBA AXIPCIeCXLAMBA
Languages:English
Tech Stack:VerilogSystemVerilogPrimeTimeTempusSDCPythonPerlTclAMBA AXIAPBPCIeCXL

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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