Low Power ASIC Engineer - New College Grad 2026
NVIDIA
Santa Clara
Workplace: OnsiteFull timeUSD 100,000 - 189,750 annuallyFunction: Energy & Utilities OperationsSkills: ["Verilog","SystemVerilog","UVM","Verdi","VCS","Incisive","DVFS","Clock gating","Power gating","GPU","ASIC"]Join NVIDIA's Low Power DV team to design and verify low-power ASICs for GPUs/SoCs. Architect/testbench development, test plans, and DV methodologies to verify power management features; collaborate with architecture, design, and software teams to enable power-efficient GPUs and drive improvements in simulation and debugging efficiency.
