Sr. Timing Methodology Engineer
AMD
San Jose
Workplace: HybridFull timeUSD 124,040 - 212,640 annuallyFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Communication","Collaboration","Problem-solving","Cross-functional collaboration","Continuous learning"]Define, develop, and drive timing and power methodologies for advanced process nodes within an Adaptive and Embedded Computing group. Partner with architecture, product planning, process, design, and product engineering teams to deliver silicon solutions with best-in-class PPA. Tackle sign-off and modeling challenges for 2nm and beyond on monolithic and 2.5/3DIC adaptive SoCs and FPGAs, working across CAD, power integrity, foundry, and EDA vendors to mitigate risks.
