Sr. Timing Methodology Engineer

AMD
San Jose
Workplace: HybridFull timeUSD 124,040 - 212,640 annuallyFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Communication","Collaboration","Problem-solving","Cross-functional collaboration","Continuous learning"]

Define, develop, and drive timing and power methodologies for advanced process nodes within an Adaptive and Embedded Computing group. Partner with architecture, product planning, process, design, and product engineering teams to deliver silicon solutions with best-in-class PPA. Tackle sign-off and modeling challenges for 2nm and beyond on monolithic and 2.5/3DIC adaptive SoCs and FPGAs, working across CAD, power integrity, foundry, and EDA vendors to mitigate risks.

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FursaFursa
AMD
AMD
1 month ago

Sr. Timing Methodology Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Define, develop, and drive timing and power methodologies for advanced process nodes within an Adaptive and Embedded Computing group. Partner with architecture, product planning, process, design, and product engineering teams to deliver silicon solutions with best-in-class PPA. Tackle sign-off and modeling challenges for 2nm and beyond on monolithic and 2.5/3DIC adaptive SoCs and FPGAs, working across CAD, power integrity, foundry, and EDA vendors to mitigate risks.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Define, develop, optimize, and drive design, timing, and power methodologies for advanced process nodes.
  • •Collaborate with implementation and sign-off teams.
  • •Collaborate with CAD, power integrity, foundry teams, and EDA vendors to understand margins and sign-off risks and develop mitigation strategies.

Pay and Benefits

Salary: USD 124,040 - 212,640 annually

Key Requirements

  • •Bachelors or Masters degree in computer engineering or Electrical Engineering.
  • •Experienced custom physical design and/or sign-off engineer.
  • •Expert user of industry-standard physical design, analysis, and sign-off tools.
  • •Experience with FPGA implementation tools.
  • •Good programming skills (Python, Perl, Tcl) and strong communication/collaboration.
Experience:SemiconductorSoCFPGA
Education:Bachelor's in computer engineering/Electrical Engineering
Skills:CommunicationCollaborationProblem-solvingCross-functional collaborationContinuous learning
Tech Stack:PythonPerlTclFPGASoCCADEDA

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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