ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX
Austin, Palo Alto
Workplace: OnsiteFull timeUSD 135,000 - 210,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 1+ yearsEducation: bachelorsSkills: ["Proactive","Intellectually curious","Team-player","Can-do attitude","Works well in a group environment"]

Develop next-generation ASICs for Starlink’s space and ground infrastructure, partnering with cross-disciplinary systems, firmware, architecture, design, validation, and ASIC implementation teams. Own scan insertion evaluation and DFT readiness, integrate and verify DFT fabrics and IP, run ATPG analysis, and debug simulations to ensure high-quality scan chains and coverage. Create ATPG content for post-silicon testing and validate it through gate-level simulation.

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FursaFursa
SpaceX
SpaceX
23 hours ago

ASIC/SOC DFT Engineer (Silicon Engineering)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Develop next-generation ASICs for Starlink’s space and ground infrastructure, partnering with cross-disciplinary systems, firmware, architecture, design, validation, and ASIC implementation teams. Own scan insertion evaluation and DFT readiness, integrate and verify DFT fabrics and IP, run ATPG analysis, and debug simulations to ensure high-quality scan chains and coverage. Create ATPG content for post-silicon testing and validate it through gate-level simulation.
Location: Austin, Palo Alto
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Entry level

Key Responsibilities

  • •Evaluate design readiness for scan insertion through RTL and physical design DRC tools
  • •Integrate and verify DFT fabrics and IP within subsystems
  • •Run and refine scan insertion through synthesis tools to maximize coverage
  • •Run and debug ATPG analysis and gate-level simulations to ensure scan chain quality and coverage
  • •Create ATPG content for post-silicon testing and collaborate with physical design, ATPG, and manufacturing teams to achieve high-quality scan coverage

Pay and Benefits

Salary: USD 135,000 - 210,000 annually
Perks:MedicalVisionDental401kDisability InsuranceLife InsuranceParental LeavePaid LeavePaid Holidays

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • •1+ years of professional experience working with ASICs
  • •Experience with scan insertion or DFT setup
  • •Understanding of ASIC design flow, methodologies, physical design, and verification
  • •Experience running scan insertion and ATPG/verification workflows to meet coverage goals
Experience:1+ yearsASICDFTSemiconductor
Education:Bachelor's
Skills:ProactiveIntellectually curiousTeam-playerCan-do attitudeWorks well in a group environment
Languages:English
Tech Stack:ASICSOCDFTScan insertionRTLPhysical designDRCATP GAutomatic Test Pattern GenerationSynthesisGate level simulationSDFVerilogSystemVerilogUPFFormal verificationScriptingCsh/bashPerlPython

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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