Physical Design Engineer (Silicon Engineering)

SpaceX
Austin, Irvine, Palo Alto
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: bachelorsSkills: ["Self-driven","Can-do attitude","Willingness to learn","Collaboration"]

Develop next-generation ASICs for SpaceX’s space and ground infrastructures supporting Starlink connectivity. You’ll perform RTL-to-GDSII physical design steps, resolve timing, congestion, and flow issues, and drive signoff closure through STA, noise, logic equivalency, and physical verification (including electromigration and voltage drop). Collaborate with ASIC design teams on feasibility and timing/power/area targets, and improve physical design methodologies and automation.

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FursaFursa
SpaceX
SpaceX
4 hours ago

Physical Design Engineer (Silicon Engineering)

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Job Summary

Develop next-generation ASICs for SpaceX’s space and ground infrastructures supporting Starlink connectivity. You’ll perform RTL-to-GDSII physical design steps, resolve timing, congestion, and flow issues, and drive signoff closure through STA, noise, logic equivalency, and physical verification (including electromigration and voltage drop). Collaborate with ASIC design teams on feasibility and timing/power/area targets, and improve physical design methodologies and automation.
Location: Austin, Irvine, Palo Alto
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •Perform partition synthesis and physical implementation steps including synthesis, floorplanning, P/G grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks.
  • •Develop and improve physical design methodologies and automation scripts for implementation steps.
  • •Collaborate with the ASIC design team on architectural feasibility studies and timing, power, and area design targets, including RTL/design tradeoffs.
  • •Resolve design/timing/congestion and flow issues, identify potential solutions, and drive execution.
  • •Run, debug, and fix signoff closure issues across STA, noise, logic equivalency, physical verification, electromigration, and voltage drop.

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • •1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development.
  • •Experience using industry standard EDA tools and understanding their capabilities and underlying algorithms.
  • •Knowledge of deep sub-micron FinFET and CMOS solid state physics.
  • •Good scripting skills for physical design automation (e.g., csh/bash, Perl, Python, TCL, Makefile).
Experience:1+ yearsASICPhysical designRTL2GDSIIEDASemiconductor
Education:Bachelor's
Skills:Self-drivenCan-do attitudeWillingness to learnCollaboration
Tech Stack:RTL2GDSIIEDAStatic timing analysis (STA)Place and routeFloorplanningLogic equivalencyElectromigrationVoltage dropCsh/bashPerlPythonTCLMakefileFinFETCMOSDFTScanMBISTLBIST

Eligibility

Nationality:US National

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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