Logic Design Engineer
Cisco
Tel Aviv
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 6+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","RTL","UVM","Verification","Timing","P&R","CAD/EDA"]Join Cisco’s Silicon One Front-End Design team to drive full-chip development, from micro-architecture and RTL design to verification and post-silicon validation. You will implement Verilog/SystemVerilog RTL, collaborate with verification and physical design teams, and contribute to timing methodologies and chip integration for cutting-edge silicon products.
