Product Engineer II - Memory IP

Cadence Design Systems
Nanjing, Shanghai
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityExperience: 2+ yearsEducation: bachelorsSkills: ["Communication","Teamwork","Problem-solving"]

Product Engineer II on Memory IP leads pre-silicon integration, QA, and post-silicon support across DDR/LPDDR/HBM/GDDR memory IPs. Acts as the primary liaison between customers, R&D, and System Validation, guiding RTL/Gate-level verification, timing closure, and documentation while collaborating with remote teams to deliver high-performance memory subsystems.

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Cadence Design Systems
Cadence Design Systems
5 months ago

Product Engineer II - Memory IP

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Product Engineer II on Memory IP leads pre-silicon integration, QA, and post-silicon support across DDR/LPDDR/HBM/GDDR memory IPs. Acts as the primary liaison between customers, R&D, and System Validation, guiding RTL/Gate-level verification, timing closure, and documentation while collaborating with remote teams to deliver high-performance memory subsystems.
Location: Nanjing, Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community

Key Responsibilities

  • •Supporting pre-silicon integration, usage, and implementation of memory subsystem products
  • •Helping with internal system integration and QA testing of memory subsystem products (Controller + PHY)
  • •Analyzing and resolving complex subsystem application or implementation issues and providing professional guidance to customers
  • •Supporting various memory PHY and controller SOC integration reviews and implementation reviews
  • •Assisting customers with RTL and gate-level simulations to verify functionality

Key Requirements

  • •B.S. Electrical/Computer Engineering (or similar) with minimum 2 years of relevant industry experience OR M.S. Electrical/Computer Engineering (or similar) degree
  • •Experience with DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 or similar IPs
  • •Verilog RTL design and gate-level verification experience
  • •Synthesis and static timing analysis experience (physical implementation/verification a plus)
  • •Familiarity with industry standard DFT flows and test methodologies
Experience:2+ yearsSemiconductorsMemory IPElectronics
Education:Bachelor's in Electrical Engineering
Skills:CommunicationTeamworkProblem-solving
Tech Stack:VerilogRTLDDR5DDR4LPDDR5HBM3GDDR6DFTSynthesisTiming analysis

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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