Cisco

3 weeks ago

System Signal & Power Integrity Hardware ASIC Simulation Engineer Lead (Remote)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Lead and advance high-performance ASIC packaging and signal/power integrity for Cisco Silicon One platforms. Drive design rules for ultra-high-speed signaling, analyze SI/PI across interposer, substrate and PCB, and mentor multidisciplinary teams while shaping processes for complex ASIC/package developments in a remote-friendly US-based role.

Location: San Jose

Workplace: Remote

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products
•Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB
•Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting
•Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules
•Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments
•Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs
•Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met
•Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams

Pay and Benefits

Salary: USD 183,800 - 263,600 annually

Perks:Health Insurance401kEquityPaid LeaveRemote Work

Key Requirements

•Bachelor's degree in Electrical Engineering with 8+ years of relevant signal and power integrity experience, or Master's degree with 6+ years, or PhD with 3+ years of experience
•High-Speed Architecture & Theory: expertise in 56G PAM4 SerDes architectures, channel modeling, BER prediction
•SI/PI Simulation Proficiency: experience with pre- and post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, Keysight ADS
•Layout Review & Physical Validation: experience with Cadence APD and Ansys EM flows for layout reviews and physical design validation
•Circuit Analysis: working knowledge of SPICE for circuit-level analysis and performance validation

Experience:SemiconductorASICSiliconHardware

Education:Bachelor's

Skills:Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM flowsSPICEPAM4Interposer2.5DUCIeHBMDie-to-die interfacesCoWoSEMIBVector Network AnalysisIBIS

Languages:English

Tech Stack:Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM flowsSPICEPAM4Interposer2.5DUCIeHBMCoWoSEMIBVector Network AnalysisIBIS

Company Brief

Cisco

Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor

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Cisco

3 weeks ago

System Signal & Power Integrity Hardware ASIC Simulation Engineer Lead (Remote)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Location: San Jose

Workplace: Remote

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products
•Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB
•Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting
•Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules
•Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments
•Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs
•Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met
•Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams

Pay and Benefits

Salary: USD 183,800 - 263,600 annually

Perks:Health Insurance401kEquityPaid LeaveRemote Work

Key Requirements

•Bachelor's degree in Electrical Engineering with 8+ years of relevant signal and power integrity experience, or Master's degree with 6+ years, or PhD with 3+ years of experience
•High-Speed Architecture & Theory: expertise in 56G PAM4 SerDes architectures, channel modeling, BER prediction
•SI/PI Simulation Proficiency: experience with pre- and post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, Keysight ADS
•Layout Review & Physical Validation: experience with Cadence APD and Ansys EM flows for layout reviews and physical design validation
•Circuit Analysis: working knowledge of SPICE for circuit-level analysis and performance validation

Experience:SemiconductorASICSiliconHardware

Education:Bachelor's

Skills:Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM flowsSPICEPAM4Interposer2.5DUCIeHBMDie-to-die interfacesCoWoSEMIBVector Network AnalysisIBIS

Languages:English

Tech Stack:Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM flowsSPICEPAM4Interposer2.5DUCIeHBMCoWoSEMIBVector Network AnalysisIBIS

Company Brief

Cisco

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor