MANAGER, DDEG DESIGN METHODOLOGY
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Communication","Collaboration"]Lead end-to-end verification methodology for complex full-chip, gate-level custom DRAM designs, including advanced low-power and power management for DDR4/LPDDR4/DDR5/LPDDR5 at high speeds. Guide verification direction, develop verification environments and cross-site methods, and advise senior management on technical issues. Drive testbench/test-vector development, run regressions, and improve debug efficiency using agentic AI-driven automation and integrated CAD/EDA/simulation workflows.
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