Senior Manager - Analog Design

AMD
Santa Clara
Workplace: HybridFull timeUSD 203,000 - 348,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsSkills: ["Analytical thinking","Inventive spirit","Risk mitigation","Communication","Team-first mindset"]

Manage the Memory I/O design team supporting the definition, specification, simulation, and implementation of future LPDDR IPs. Lead circuit architecture and low-power, area-efficient analog/digital blocks for LPDDR PHYs, coordinating Analog Mixed Signal, Digital, Firmware, and Design Verification to deliver optimal PHY performance. Drive model development for link-level statistical simulations (training, equalization, calibration) and guide micro-architecture documentation and development-flow improvements across teams.

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FursaFursa
AMD
AMD
1 day ago

Senior Manager - Analog Design

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Source: Company careers pageValidated by: Fursa AI
Last checked: 14 hours agoStatus: Live

Job Summary

Manage the Memory I/O design team supporting the definition, specification, simulation, and implementation of future LPDDR IPs. Lead circuit architecture and low-power, area-efficient analog/digital blocks for LPDDR PHYs, coordinating Analog Mixed Signal, Digital, Firmware, and Design Verification to deliver optimal PHY performance. Drive model development for link-level statistical simulations (training, equalization, calibration) and guide micro-architecture documentation and development-flow improvements across teams.
Location: Santa Clara
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Manage and contribute to the definition of circuit architecture and design implementation of low power, area efficient blocks for LPDDR PHYs.
  • •Collaborate across Analog Mixed Signal, Digital Design, Firmware, and Design Verification to ensure optimal PHY architecture and feature coverage.
  • •Manage execution and deliverables across customers and stakeholders.
  • •Develop link-level statistical performance simulation models for the PHY (including training, equalization, and calibration) to guide design development and optimization.
  • •Document micro-architecture and algorithms and provide guidance to Analog, Digital, Firmware, and Verification teams; contribute to development flows to improve efficiency and quality.

Pay and Benefits

Salary: USD 203,000 - 348,000 annually

Key Requirements

  • •Minimum 5+ years of team management experience leading multiple IPs from design to production.
  • •Proven track record leading execution of multiple PHY designs with strong silicon results.
  • •Strong circuit-architecture and modeling experience for high-speed I/Os, including equalization, calibration, and clocking techniques.
  • •Hands-on knowledge of PHY modeling tools and best practices, including Matlab/Simulink and Verilog/AMS-based approaches.
  • •Solid knowledge of IO and system integration (signaling/equalization, signal integrity, power integrity) and ability to dig into RTL or firmware code.
Experience:5+ years
Education:
Skills:Analytical thinkingInventive spiritRisk mitigationCommunicationTeam-first mindset
Languages:En-us
Tech Stack:LPDDRMatlabSimulinkVerilogAMSRTLFirmwareLink TrainingEqualizationCalibrationClocking

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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