Samsung

6 months ago

Sr. Staff Physical Design PPA Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Senior-level hardware/IC design engineer leading Power/Performance/Area initiatives for Physical Design at Samsung’s SARC/ACL labs. Drives design flows, automates PPA methodologies, and oversees end-to-end IP block implementation from synthesis to signoff, collaborating with RTL and SOC teams to ensure frequency, power, and area targets are met for premium IPs used in high-performance computing devices.

Location: Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Lead PPA initiatives by identifying opportunities, tracking progress, and executing towards delivering solutions that meet project requirements
•Drive flows and methodologies improvements for automating Physical Design Implementation, collaborating with stakeholders to ensure that solutions meet their needs and expectations
•Hands-on responsibility from synthesis to place and route of an IP block through signoff flows, including timing and physical verification
•Interact with RTL counterparts and SOC teams to resolve design issues pertaining to block closure, providing feedback and working together to optimize the design flow
•Ensure that designs meet PPA targets and signoff requirements with high quality deliverables

Pay and Benefits

Perks:MedicalDentalVision401k

Key Requirements

•10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD
•Solid understanding of the SOC/ASIC design flow with particular experience in taping out designs
•Experience with synthesis, block, and full chip implementation utilizing the latest industry P&R/STA flows and tools
•Experience in block level floor-planning, implementing power grid and area/congestion optimization
•Proficient scripting/programming skills in TCL, Perl, Shell, and/or Python

Experience:10+ yearsSemiconductorsGPUIP

Skills:TCLPerlShellPythonScriptingSynthesisPlace & RouteCTS

Tech Stack:TCLPerlShellPythonSynthesisPlace&RouteCTSTimingPowerArea

Company Brief

Samsung

Global conglomerate known for consumer electronics, home appliances, semiconductors, displays, and mobile devices. Designs and manufactures a wide range of products and solutions for consumers, enterprises, and industrial customers worldwide.

Industry: Conglomerates & Holding Companies

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Seoul, South Korea

Founded: 1938

Glassdoor: 3.7

Website LinkedIn

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Samsung

6 months ago

Sr. Staff Physical Design PPA Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Lead PPA initiatives by identifying opportunities, tracking progress, and executing towards delivering solutions that meet project requirements
•Drive flows and methodologies improvements for automating Physical Design Implementation, collaborating with stakeholders to ensure that solutions meet their needs and expectations
•Hands-on responsibility from synthesis to place and route of an IP block through signoff flows, including timing and physical verification
•Interact with RTL counterparts and SOC teams to resolve design issues pertaining to block closure, providing feedback and working together to optimize the design flow
•Ensure that designs meet PPA targets and signoff requirements with high quality deliverables

Pay and Benefits

Perks:MedicalDentalVision401k

Key Requirements

•10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD
•Solid understanding of the SOC/ASIC design flow with particular experience in taping out designs
•Experience with synthesis, block, and full chip implementation utilizing the latest industry P&R/STA flows and tools
•Experience in block level floor-planning, implementing power grid and area/congestion optimization
•Proficient scripting/programming skills in TCL, Perl, Shell, and/or Python

Experience:10+ yearsSemiconductorsGPUIP

Skills:TCLPerlShellPythonScriptingSynthesisPlace & RouteCTS

Tech Stack:TCLPerlShellPythonSynthesisPlace&RouteCTSTimingPowerArea

Company Brief

Samsung

Industry: Conglomerates & Holding Companies

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Seoul, South Korea

Founded: 1938

Glassdoor: 3.7

Website LinkedIn