AI Silicon, Junior Digital Design Engineer

Unconventional AI
Palo Alto
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","RTL","EDA tools","VLSI","Clock domain crossing","LEC","CDC","UVM"]

Foundational member of a small multi-disciplinary R&D team focusing on SOC design for an AI accelerator. You will contribute to micro-architecture, write Verilog/SystemVerilog RTL, perform synthesis and timing, verify designs, and collaborate with internal design and physical implementation teams to drive invention and prototyping of a novel computing platform.

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FursaFursa
Unconventional AI
Unconventional AI
2 months ago

AI Silicon, Junior Digital Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Foundational member of a small multi-disciplinary R&D team focusing on SOC design for an AI accelerator. You will contribute to micro-architecture, write Verilog/SystemVerilog RTL, perform synthesis and timing, verify designs, and collaborate with internal design and physical implementation teams to drive invention and prototyping of a novel computing platform.
Location: Palo Alto
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •SoC Design & Integration: Contribute to the micro-architecture definition and integration of digital blocks, including CPU, interfaces and memory subsystems; assist in the integration of third-party IP into the main SoC fabric.
  • •Hands-on RTL Implementation: Write clean, synthesizable Verilog/SystemVerilog code; perform RTL design for SoC blocks and digital interfaces to meet power, performance, and area targets; implement and debug key digital interfaces for system stability; implement low-power techniques (clock gating, power domains).
  • •Synthesis & Timing: Perform initial synthesis and formal verification (LEC) to ensure routability and target frequencies; create block-level timing constraints; run RTL linting, CDC/ RDC checks using industry-standard tools.
  • •Design Verification (DV) Support: Participate in the verification plan and help develop a robust verification environment; triage and debug simulation failures to ensure functional correctness.
  • •External Coordination: Support technical interfaces and assist in hand-off between internal design and physical implementation teams.

Pay and Benefits

Perks:Health Insurance401kPaid LeaveMeal Allowance

Key Requirements

  • •BS or MS in Electrical Engineering, Computer Engineering, or a related field.
  • •4+ years of industry experience in digital ASIC/SoC design.
  • •Strong technical expertise in Verilog RTL coding and digital design fundamentals.
  • •Familiarity with standard EDA tools for simulation, assertions, synthesis, linting, and clock domain crossing (CDC) analysis.
  • •Understanding of the full ASIC design flow, from specification to tape-out.
Experience:4+ yearsASICSoCDigital designSemiconductors
Education:Bachelor's
Skills:VerilogSystemVerilogRTLEDA toolsVLSIClock domain crossingLECCDCUVM
Languages:English
Tech Stack:VerilogSystemVerilogRTLEDA toolsVLSIClock domain crossingLECCDCUVM

Company Brief

Unconventional AI
Builds customizable AI copilots and fine-tuned large language model solutions to help teams automate workflows, surface actionable insights, and integrate generative AI into business processes across products and operations.
Industry: AI & Machine Learning
Company Size: Small (11 to 50 employees)
Growth: Early Stage Startup
Funding: Seed
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