5 days ago

Senior ASIC Design Engineer

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Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Join the R&D digital ASIC design team developing core controller ASICs and HP proprietary IP for future printers. Lead RTL coding through verification, silicon validation, and qualification, while partnering with internal and external teams to align specs, drive reviews, and document outcomes. Contribute to print architecture and data-path requirements, prototype ASIC designs in FPGA or models, and help advance design methodology and tool automation.

Location: Vancouver, Washington

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Lead functional blocks and/or subsystems of digital ASICs from design through silicon verification, including RTL coding, verification, silicon validation, and qualification.
•Work with team members and partners to align on specifications, drive design reviews, and complete documentation.
•Manage and expand relationships with internal and external development partners.
•Contribute to ASIC roadmaps and future innovation, including cross-discipline task forces to triage product HW/FW integration issues.
•Contribute to inkjet and laserjet print architecture and data path requirements and support pre-silicon firmware development via FPGA/software model prototyping.

Pay and Benefits

Salary: USD 116,150 - 182,400 annually

Equity and Bonus:Equity

Perks:Health InsuranceDentalVisionDisability InsuranceLife InsuranceEmployee AssistanceFlexible SpendingParental LeavePaid Holidays

Key Requirements

•BS or MS in electrical engineering (or equivalent) with VLSI design focus.
•8–10 years of ASIC or SoC design and development experience.
•Deep knowledge of submicron semiconductor technology and the digital ASIC/SoC design flow from RTL to silicon characterization.
•Strong familiarity with embedded system design, verification, and the product development lifecycle.
•Proficiency with Verilog/SystemVerilog and common coding/verification languages and flows (e.g., Synopsys/Cadence EDA for simulation, synthesis, STA, formal and assertion-based verification).

Experience:8-10 yearsASICSoCSemiconductorsEmbedded systemsDigital designEmbedded verification

Education:Master's in Electrical engineering

Skills:Analytical and problem-solvingWritten and verbal communicationCross-team collaborationRelationship managementDocumentation and review leadership

Tech Stack:ASIC designSoCVerilogSystemVerilogSVRTLSynopsysCadence EDASimulationSynthesisSTAFormal verificationAssertion-based verificationPythonPerlCC++SubversionGitGitHub

Company Brief

Designs and manufactures personal computers, printers, and related supplies, as well as provides software, services, and solutions for consumers and enterprises worldwide.

Industry: Hardware Devices

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Palo Alto, United States

Founded: 1939

Glassdoor: 3.8

Website LinkedIn

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