Physical Design Engineer

Own RTL-to-GDSII implementation for advanced semiconductor nodes (sub-16nm to 3nm), including hierarchical floorplanning, place and route, clock/power distribution, and timing convergence. Run static timing analysis (multi-mode/multi-corner), build automation scripts in STA tools, and manage timing ECOs using Tweaker/PrimeTime. Analyze quality/efficiency gaps, improve backend design flows, and collaborate with RTL, DFT, EDA vendors, and tool owners to deliver high-performance networking chips.