Lead Design Engineer - Physical Design

Cadence Design Systems
Beijing
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: mastersSkills: ["Perl","C shell","TCL","Makefile","Python","Innovus","ICC","Calibre","Tempus","PrimeTime"]

Lead Design Engineer responsible for high speed digital DDR and HBM IP physical implementation, developing scripts/tools to enhance the PD design flow, and driving design optimization across projects. You will contribute to floorplanning, CTS, STA, and physical verification, collaborate in product projects, and summarize PPA methodologies to implement optimal design parameters for multiple nodes and processes.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
4 months ago

Lead Design Engineer - Physical Design

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Lead Design Engineer responsible for high speed digital DDR and HBM IP physical implementation, developing scripts/tools to enhance the PD design flow, and driving design optimization across projects. You will contribute to floorplanning, CTS, STA, and physical verification, collaborate in product projects, and summarize PPA methodologies to implement optimal design parameters for multiple nodes and processes.
Location: Beijing
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Focus on high speed digital DDR and HBM IP physical implementation
  • •Develop necessary scripts or tools to enhance current PD design flow
  • •Work in product projects, including completing tasks and solving design issues while providing flow to check and avoid similar issues
  • •Analyze and summarize PPA optimization methodologies and results
  • •Implement optimal design parameters and flows for different projects

Key Requirements

  • •MS in EE with at least 3 years relevant IC design experience
  • •Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis
  • •Solid background in circuits, electronics, physics, willing to learn new technology for cutting edge process node and advanced design methodology
  • •Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python
  • •Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime, etc.
Experience:3+ yearsIC designSemiconductors
Education:Master's in Electrical Engineering
Skills:PerlC shellTCLMakefilePythonInnovusICCCalibreTempusPrimeTime
Tech Stack:PerlPythonTCLInnovusCalibreTempusPrimeTimeMakefileShell

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor