MTS DRAM ASIC Architect

Micron Technology
Bengaluru
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 5+ yearsEducation: bachelorsSkills: ["Cross-functional collaboration","Analytical thinking","Problem-solving","Communication","Architectural tradeoff decision-making"]

Architect next-generation DRAM products that combine advanced CMOS logic die technologies with DRAM functionality across LPDDR, DDR, and HBM. Define DRAM + logic-die system and subsystem architectures, including functional partitioning, high-performance I/O interfaces, reliability and manageability features, and test/monitoring paths. Drive tradeoff-based decisions across area, power, latency, yield, and scalability while partnering with DRAM design, ASIC architecture, packaging, process, validation, firmware, and systems teams.

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FursaFursa
Micron Technology
Micron Technology
3 weeks ago

MTS DRAM ASIC Architect

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Job Summary

Architect next-generation DRAM products that combine advanced CMOS logic die technologies with DRAM functionality across LPDDR, DDR, and HBM. Define DRAM + logic-die system and subsystem architectures, including functional partitioning, high-performance I/O interfaces, reliability and manageability features, and test/monitoring paths. Drive tradeoff-based decisions across area, power, latency, yield, and scalability while partnering with DRAM design, ASIC architecture, packaging, process, validation, firmware, and systems teams.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Define next-generation DRAM + logic-die architectures, including functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms to optimize performance, power, cost, reliability, and differentiation.
  • •Identify and evaluate system, interface, reliability, test, management, and control functions suited for advanced logic-die implementations, performing architectural tradeoff analysis across area, power, latency, yield, testability, reliability, and scalability.
  • •Architect scalable CMOS logic-die subsystem solutions using custom, semi-custom, and standard IP components.
  • •Architect high-performance interfaces between DRAM die and logic die, including command, data, clocking, synchronization, test, monitoring, and management paths.
  • •Identify emerging opportunities and influence roadmaps for advanced memory system capabilities.

Key Requirements

  • •BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related fields with 5+ years of experience in semiconductor architecture, design, or system engineering.
  • •Experience in one or more of: DRAM architecture, memory subsystem architecture, ASIC/SoC architecture.
  • •Strong understanding of DRAM architecture, including command flows, timing behavior, bank architecture, refresh management, row-hammer mitigation, and reliability features.
  • •Exposure to high-speed I/O and PHY architectures, clocking systems, SI/PI considerations, power delivery, thermal design, and/or die-to-die interfaces.
  • •Ability to lead cross-functional technical discussions and drive tradeoff-based architectural decision making with strong written and verbal communication.
Experience:5+ yearsSemiconductorsDRAMMemory systemsASIC/SoCHigh-speed I/O
Education:Bachelor's
Skills:Cross-functional collaborationAnalytical thinkingProblem-solvingCommunicationArchitectural tradeoff decision-making
Tech Stack:DRAM architectureCMOSLogic dieLPDDRDDRHBMDDR5DDR6LPDDR5LPDDR6GDDRASICSoCI/O architecturePHYClockingSI/PIPower deliveryThermal designDie-to-die interfaces

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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