Digital IC Backend Design Engineer

Arago
Paris, Tel Aviv
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4+ yearsEducation: mastersSkills: ["Collaboration","Teamwork","Problem-solving","Communication","Attention to detail"]

Join a fast-paced, engineering-led team to drive the physical implementation of digital IC designs from RTL to GDSII. Collaborate with RTL, DFT, and packaging teams to optimize performance, power, and area, while ensuring timing and yield targets across full-chip and block-level designs. You'll work with Cadence Innovus/Genus, Tcl scripting, and advanced nodes to enable reliable tapeouts and growth in a cutting-edge AI hardware company.

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FursaFursa
Arago
Arago
1 year ago

Digital IC Backend Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Join a fast-paced, engineering-led team to drive the physical implementation of digital IC designs from RTL to GDSII. Collaborate with RTL, DFT, and packaging teams to optimize performance, power, and area, while ensuring timing and yield targets across full-chip and block-level designs. You'll work with Cadence Innovus/Genus, Tcl scripting, and advanced nodes to enable reliable tapeouts and growth in a cutting-edge AI hardware company.
Location: Paris, Tel Aviv
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and physical verification.
  • •Develop and optimize the digital backend flow.
  • •Drive timing closure, power optimization, and physical verification (LVS/DRC/ERC).
  • •Collaborate with front-end designers to address timing and logical/physical interface issues.
  • •Support tapeout preparation and final signoff processes.

Pay and Benefits

Perks:EquityHealth InsurancePensionRelocationPaid Leave

Key Requirements

  • •Master’s or PhD degree in Electrical/Electronic Engineering or a related field.
  • •4+ years experience in digital IC backend implementation.
  • •Proficiency with backend EDA tools, particularly Cadence Innovus and Genus.
  • •Strong understanding of place & route (P&R), static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.
  • •Experience with advanced technology nodes (22nm or below preferred).
Experience:4+ years
Education:Master's
Skills:CollaborationTeamworkProblem-solvingCommunicationAttention to detail
Languages:EnglishFrench
Tech Stack:Cadence InnovusCadence GenusTclP&RSTADRCLVSEMIR drop

Company Brief

Arago
Develops energy-efficient photonic AI processors (codenamed “JEF”) that use light-based computation to drastically reduce energy consumption for AI workloads, targeting data centers and large-scale inference deployments.
Industry: Deep Tech
Company Size: Small (11 to 50 employees)
Growth: Early Stage Startup
Funding: Seed
Headquarters: Paris, France
Founded: 2024
Glassdoor
Glassdoor: 3.9
WebsiteGlassdoor