NVIDIA

4 weeks ago

Senior Power Integrity Co-Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 2 hours agoStatus: Live

Job Summary

Senior Power Integrity Co-Design Engineer to architect and mitigate di/dt noise across silicon, package, board, and platform; bridging architecture, silicon, and platform to translate product noise targets into shipped specs, while applying AI to enhance analysis with rigorous engineering judgment.

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them.
•Co-design noise features with Speed, Power, Reliability, Circuit Design, Power-Arch, ASIC, and platform teams; you’re the connective tissue across the codesign web.
•Define product-level voltage noise targets, drive them to closure, and sign them off at shipment.
•Build and own the Sim-to-Si correlation methodology for noise; you know when a model is lying and when silicon is.
•Model and prototype next-gen noise features and codify them so every future program inherits them.

Pay and Benefits

Salary: USD 136,000 - 218,500 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•BS / MS / PhD in EE, CE, or related (or equivalent experience).
•5+ years in silicon power integrity, voltage noise, or PDN.
•Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, decap budgeting, voltage regulator response.
•Hands-on silicon experience: bringup, characterization, correlation. Comfortable on a bench with scopes, probes, DAQ — and in front of a simulator.
•Strong Sim-to-Si correlation instincts — the field of figuring out which side of the equals sign is wrong.

Experience:SemiconductorElectronicsHardware

Languages:English

Tech Stack:Di/dt analysisPDN designVoltage noiseSimulationBench oscilloscopeDAAAIMachine learningVoltage regulatorNoise modeling

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

4 weeks ago

Senior Power Integrity Co-Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 2 hours agoStatus: Live

Job Summary

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them.
•Co-design noise features with Speed, Power, Reliability, Circuit Design, Power-Arch, ASIC, and platform teams; you’re the connective tissue across the codesign web.
•Define product-level voltage noise targets, drive them to closure, and sign them off at shipment.
•Build and own the Sim-to-Si correlation methodology for noise; you know when a model is lying and when silicon is.
•Model and prototype next-gen noise features and codify them so every future program inherits them.

Pay and Benefits

Salary: USD 136,000 - 218,500 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•BS / MS / PhD in EE, CE, or related (or equivalent experience).
•5+ years in silicon power integrity, voltage noise, or PDN.
•Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, decap budgeting, voltage regulator response.
•Hands-on silicon experience: bringup, characterization, correlation. Comfortable on a bench with scopes, probes, DAQ — and in front of a simulator.
•Strong Sim-to-Si correlation instincts — the field of figuring out which side of the equals sign is wrong.

Experience:SemiconductorElectronicsHardware

Languages:English

Tech Stack:Di/dt analysisPDN designVoltage noiseSimulationBench oscilloscopeDAAAIMachine learningVoltage regulatorNoise modeling

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor