Lead RTL Design Engineer

Cerebras
Sunnyvale
Workplace: OnsiteFull timeUSD 175,000 - 275,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8-15 yearsEducation: mastersSkills: ["Collaboration","Vendor management","Debugging","Cross-functional communication"]

Design and develop next-generation wafer-scale engine (WSE) hardware, driving RTL development from functional specification through micro-architecture and synthesis. Collaborate with design verification, DFT, physical design, and software/system teams to achieve performance, power, and scalable chip integration goals. Manage external ASIC vendors across the product development cycle and debug silicon-level functional, timing, and power issues during bring-up.

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FursaFursa
Cerebras
Cerebras
10 months ago

Lead RTL Design Engineer

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Last checked: 16 hours agoStatus: Live

Job Summary

Design and develop next-generation wafer-scale engine (WSE) hardware, driving RTL development from functional specification through micro-architecture and synthesis. Collaborate with design verification, DFT, physical design, and software/system teams to achieve performance, power, and scalable chip integration goals. Manage external ASIC vendors across the product development cycle and debug silicon-level functional, timing, and power issues during bring-up.
Location: Sunnyvale
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive chip design activities including functional specification, micro-architecture, RTL development, and synthesis.
  • •Manage external ASIC vendors throughout the product development cycle.
  • •Support design closure with PD team members to meet PPA goals.
  • •Partner with design verification and DFT teams to achieve functional and test coverage.
  • •Debug silicon-level functional, timing, and power issues during bring-up and work with software/system teams to improve performance and features.

Pay and Benefits

Salary: USD 175,000 - 275,000 annually
Equity and Bonus:Equity
Perks:Annual BonusEquity

Key Requirements

  • •Master’s degree in Computer Science, Electrical Engineering, or equivalent.
  • •8–15 years delivering complex, high-performance RTL designs.
  • •Experience with front-end chip integration and third-party IP integration.
  • •Demonstrated expertise in networking, high-performance computing, machine learning, or related fields.
  • •Working knowledge of Python and TCL scripting tools, plus networking stack experience (TCP/IP, RDMA, Ethernet) and familiarity with PCIe, CPU interfaces, and Serdes.
Experience:8-15 years
Education:Master's
Skills:CollaborationVendor managementDebuggingCross-functional communication
Tech Stack:RTLMicro-architectureSynthesisFunctional specificationASIC vendor managementDFTDesign verificationPhysical designTCP/IPRDMAEthernetPCIeSerdesCPU interfacesPythonTCLFPGAPlace and RouteFloor planningTiming analysis

Company Brief

Cerebras
Designs and builds wafer-scale AI accelerators and systems for large-scale deep learning workloads, delivering specialized hardware and software to accelerate model training and inference for enterprises and research institutions.
Industry: Hardware Devices
Company Size: Large (251 to 1,000 employees)
Growth: Scaleup
Headquarters: Sunnyvale, United States
Founded: 2016
WebsiteLinkedIn