Intel

20 hours ago

Analog Layout Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 20 hours agoStatus: Live

Job Summary

Design and optimize complex analog signal circuit layouts that underpin Intel’s advanced products. Own layout execution and verification, including DRC, electrical reliability checks, and validation of voltage drop, electron migration, and ESD. Develop floorplans, power grids, ESD structures, and routing for performance, area, and reliability, while performing microfloor planning and troubleshooting tool and methodology issues to improve productivity and quality.

Location: Penang

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Design complex layouts of analog signal circuits based on design specifications.
•Execute full design verification, including process design rule checks, electrical reliability checks, and validation of voltage drop (IR), electron migration, and ESD.
•Develop and analyze floorplans, power grids, ESD structures, and signal routing to meet performance, area, and reliability requirements.
•Perform microfloor planning and detailed signal planning to ensure critical signals meet electrical constraints like shielding and signal matching.
•Troubleshoot analog layout design and tool/flow/methodology issues, and collaborate cross-functionally to implement approaches that improve layout productivity, quality, and reliability.

Key Requirements

•Bachelor’s degree in Electrical Engineering, Electronics, or related field with 4+ years of industry experience, or a Master’s with 2+ years, or a PhD with relevant knowledge.
•Proficiency in analog layout design fundamentals, including analog/mixed-signal concepts and CMOS technologies.
•Hands-on experience with EDA tools such as Cadence Virtuoso Layout Suite and Calibre DRC, plus extraction/debug tools.
•Expertise in floor planning, hierarchical layout planning, and routing for analog/mixed-signal blocks.
•Familiarity with reliability verification, including high-voltage rules and electronic interconnect reliability.

Experience:4+ years

Education:Bachelor's in Electrical Engineering, Electronics, or related field

Skills:Problem-solvingTroubleshootingTechnical documentationCollaborationCommunication

Tech Stack:Cadence Virtuoso Layout SuiteCalibre DRCEDA toolsExtraction/debug toolsCMOS

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

20 hours ago

Analog Layout Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 20 hours agoStatus: Live

Job Summary

Location: Penang

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Design complex layouts of analog signal circuits based on design specifications.
•Execute full design verification, including process design rule checks, electrical reliability checks, and validation of voltage drop (IR), electron migration, and ESD.
•Develop and analyze floorplans, power grids, ESD structures, and signal routing to meet performance, area, and reliability requirements.
•Perform microfloor planning and detailed signal planning to ensure critical signals meet electrical constraints like shielding and signal matching.
•Troubleshoot analog layout design and tool/flow/methodology issues, and collaborate cross-functionally to implement approaches that improve layout productivity, quality, and reliability.

Key Requirements

•Bachelor’s degree in Electrical Engineering, Electronics, or related field with 4+ years of industry experience, or a Master’s with 2+ years, or a PhD with relevant knowledge.
•Proficiency in analog layout design fundamentals, including analog/mixed-signal concepts and CMOS technologies.
•Hands-on experience with EDA tools such as Cadence Virtuoso Layout Suite and Calibre DRC, plus extraction/debug tools.
•Expertise in floor planning, hierarchical layout planning, and routing for analog/mixed-signal blocks.
•Familiarity with reliability verification, including high-voltage rules and electronic interconnect reliability.

Experience:4+ years

Education:Bachelor's in Electrical Engineering, Electronics, or related field

Skills:Problem-solvingTroubleshootingTechnical documentationCollaborationCommunication

Tech Stack:Cadence Virtuoso Layout SuiteCalibre DRCEDA toolsExtraction/debug toolsCMOS

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor