Senior RTL Design Engineer

Cisco
Armenia
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 6+ yearsSkills: ["Mentoring","Communication","Self-motivation","Organizational skills"]

Shape next-generation silicon architecture by contributing across the full ASIC digital design flow, from micro-architecture through RTL design and qualification. Lead RTL code review and enhancements, support sub-system/SoC integration and verification, and improve IP/SoC methodologies and flows. Partner with verification and physical design teams to debug failures and improve physical design QoR. Serve as a technical leader, mentoring engineers and influencing physical design strategies.

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FursaFursa
Cisco
Cisco
6 months ago

Senior RTL Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Shape next-generation silicon architecture by contributing across the full ASIC digital design flow, from micro-architecture through RTL design and qualification. Lead RTL code review and enhancements, support sub-system/SoC integration and verification, and improve IP/SoC methodologies and flows. Partner with verification and physical design teams to debug failures and improve physical design QoR. Serve as a technical leader, mentoring engineers and influencing physical design strategies.
Location: Armenia
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Contribute across digital design from micro-architecture through RTL design and qualification.
  • •Drive sub-system/SoC integration and verification activities.
  • •Review and enhance RTL code.
  • •Improve flows and methodologies to streamline IP/SoC development and integration.
  • •Collaborate closely with verification and physical design teams to resolve debug issues and improve physical design QoR.

Key Requirements

  • •6+ years of industry experience in ASIC digital design.
  • •Proficiency in Verilog/SystemVerilog coding.
  • •Experience with front-end tools including simulators, linting, CDC checkers, synthesis, and formal verification.
  • •Experience with industry interface protocols such as AMBA (AXI, APB, AHB), JTAG, and memories.
  • •Ability to write scripts using Python, Tcl, and Make.
Experience:6+ yearsASICSemiconductors
Skills:MentoringCommunicationSelf-motivationOrganizational skills
Tech Stack:VerilogSystemVerilogPythonTclMakeAMBAAXIAPBAHBJTAGUPFDFTMBIST

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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