Substrate Design Engineer

Cisco
Taipei
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Collaboration","Communication","Self-motivation","Attention to detail","Ownership mindset"]

Design advanced ASIC package substrates and layouts for next-generation Cisco optical products, taking concepts from early planning and floor planning through implementation, verification, and tape out. Work with system, hardware, SI/PI, silicon, thermal, mechanical, and manufacturing teams to deliver high-speed, robust, manufacturable package solutions. Use Cadence Allegro Package Designer and Cadence SiP Layout to perform routing, rule checking, DRC resolution, and design release documentation for fabrication and assembly.

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FursaFursa
Cisco
Cisco
6 days ago

Substrate Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Design advanced ASIC package substrates and layouts for next-generation Cisco optical products, taking concepts from early planning and floor planning through implementation, verification, and tape out. Work with system, hardware, SI/PI, silicon, thermal, mechanical, and manufacturing teams to deliver high-speed, robust, manufacturable package solutions. Use Cadence Allegro Package Designer and Cadence SiP Layout to perform routing, rule checking, DRC resolution, and design release documentation for fabrication and assembly.
Location: Taipei
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Create and maintain advanced substrate layouts for BGA, flip-chip, SiP, multi-die packages, and HDI/mSAP PCBs.
  • •Perform substrate floor planning, bump/ball map implementation, pinout optimization, stack-up implementation, and routing planning.
  • •Use Cadence Allegro Package Designer and Cadence SiP Layout for routing, rule checking, and design release.
  • •Implement routing for high-speed signals and power/ground networks while meeting SI/PI, impedance, spacing, via, and manufacturing constraints.
  • •Set up and resolve package-level design rules/DRC issues and support DFM/DFT, fabrication, assembly, tape out, and package bring-up activities.

Key Requirements

  • •Bachelor’s degree with 5+ years experience (or Master’s degree with 3+ years) in Electrical Engineering, Packaging Engineering, or related field.
  • •Hands-on experience with Cadence Allegro Package Designer and Cadence SiP Layout.
  • •Understanding of package substrate technologies, layer stack-ups, routing constraints, via structures, power/ground distribution, and controlled impedance.
  • •Experience routing high-speed signals, differential pairs, power, and ground networks.
  • •Experience with design rule setup, DRC resolution, layout verification, and design release for fabrication and assembly.
Experience:5+ yearsOptical productsASIC packagingSemiconductorsHigh-speed design
Education:Bachelor's in Electrical Engineering
Skills:CollaborationCommunicationSelf-motivationAttention to detailOwnership mindset
Tech Stack:Cadence Allegro Package DesignerCadence SiP LayoutCadence Allegro platformPCB EditorXtractIMPowerSIHFSSDRCDFMSiPHDIMSAPBGAFlip-chip

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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