3 months ago

Senior/Staff Design for Test Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Senior/Staff DFT engineer leading end-to-end test strategy and implementation for high-throughput ASICs/SoCs, driving DFT architecture, verification, and integration with cross-functional teams to deliver high fault coverage and robust silicon bring-up.

Location: Bristol

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Architect, own, and implement the comprehensive DFT strategy for complex high-throughput digital pipelines in advanced CMOS nodes, ensuring high test coverage and efficient test execution.
•Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST, ensuring adherence to industrial standards and sign-off criteria.
•Partner with the test engineering team to develop, validate, and optimize ATE-compatible test patterns (stuck-at, transition, bridging, etc.) to achieve aggressive fault coverage and maximise manufacturing yield.
•Drive RTL development (SystemVerilog/Verilog/VHDL) with a focus on DFT architecture, including synthesis constraints for test structures, and collaborate on formal and constrained-random verification of DFT logic.
•Analyse and minimise the DFT impact on power, performance, and area (PPA), implementing innovative techniques for efficient test access and execution.

Pay and Benefits

Equity and Bonus:Equity

Perks:Health InsuranceEquity

Key Requirements

•7+ years of hands-on DFT architecture, implementation, and verification for high-performance ASICs/SoCs, with ownership of a product and comprehensive DFT coverage.
•Proven success implementing and verifying advanced DFT features (e.g., Scan/ATPG, Boundary Scan, Memory BIST/Repair) across multi-hundred-MHz to multi-GHz clock domains.
•Expertise with industry-standard EDA flows: scan insertion, ATPG, gate-level pattern simulation, fault modeling, and diagnosis tools.
•Demonstrated proficiency with DFT flows: compression techniques, EDT, JTAG/IEEE 1149.1/1687, and managing large pattern sets.
•Proficiency using Python/Tcl scripting for DFT flow automation, pattern generation/management, and silicon debug/bring-up.

Experience:7+ yearsSemiconductorsASICsSoCsAI hardware

Skills:SystemVerilogVerilogVHDLPythonTclDFTATPGScanJTAGMemory BISTPattern generationEDA tools

Languages:English

Tech Stack:SystemVerilogVerilogVHDLPythonTclJTAGATPGMemory BISTScan

Company Brief

Olix

Olix designs and manufactures optical processors (Optical Tensor Processing Units) for training and running inference on large AI models, aiming to deliver higher performance and lower energy consumption than conventional silicon-based accelerators.

Industry: Deep Tech

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Headquarters: London, United Kingdom

Founded: 2024

Glassdoor: 3.0

Website LinkedIn Glassdoor

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Olix

3 months ago

Senior/Staff Design for Test Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Location: Bristol

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Architect, own, and implement the comprehensive DFT strategy for complex high-throughput digital pipelines in advanced CMOS nodes, ensuring high test coverage and efficient test execution.
•Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST, ensuring adherence to industrial standards and sign-off criteria.
•Partner with the test engineering team to develop, validate, and optimize ATE-compatible test patterns (stuck-at, transition, bridging, etc.) to achieve aggressive fault coverage and maximise manufacturing yield.
•Drive RTL development (SystemVerilog/Verilog/VHDL) with a focus on DFT architecture, including synthesis constraints for test structures, and collaborate on formal and constrained-random verification of DFT logic.
•Analyse and minimise the DFT impact on power, performance, and area (PPA), implementing innovative techniques for efficient test access and execution.

Pay and Benefits

Equity and Bonus:Equity

Perks:Health InsuranceEquity

Key Requirements

•7+ years of hands-on DFT architecture, implementation, and verification for high-performance ASICs/SoCs, with ownership of a product and comprehensive DFT coverage.
•Proven success implementing and verifying advanced DFT features (e.g., Scan/ATPG, Boundary Scan, Memory BIST/Repair) across multi-hundred-MHz to multi-GHz clock domains.
•Expertise with industry-standard EDA flows: scan insertion, ATPG, gate-level pattern simulation, fault modeling, and diagnosis tools.
•Demonstrated proficiency with DFT flows: compression techniques, EDT, JTAG/IEEE 1149.1/1687, and managing large pattern sets.
•Proficiency using Python/Tcl scripting for DFT flow automation, pattern generation/management, and silicon debug/bring-up.

Experience:7+ yearsSemiconductorsASICsSoCsAI hardware

Skills:SystemVerilogVerilogVHDLPythonTclDFTATPGScanJTAGMemory BISTPattern generationEDA tools

Languages:English

Tech Stack:SystemVerilogVerilogVHDLPythonTclJTAGATPGMemory BISTScan

Company Brief

Olix

Industry: Deep Tech

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Headquarters: London, United Kingdom

Founded: 2024

Glassdoor: 3.0

Website LinkedIn Glassdoor