Senior ASIC Timing Engineer

NVIDIA
Durham
Workplace: OnsiteFull timeUSD 168,000 - 264,500 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: bachelorsSkills: ["Teamwork","Communication","Problem-solving"]

Senior ASIC Timing Engineer to drive physical design and timing of high-frequency DPUs/SoCs, optimizing constraints and synthesis parameters to hit performance, power, and area targets. You’ll handle RTL-to-GDS2 flows, ECOs, floorplanning, and timing convergence, leveraging STA, LEC, and industry EDA tools (PrimeTime/Tempus). Strong Python/Tcl/Make automation and a background in Synthesis & Timing are required.

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FursaFursa
NVIDIA
NVIDIA
6 months ago

Senior ASIC Timing Engineer

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Last checked: 5 hours agoStatus: Live

Job Summary

Senior ASIC Timing Engineer to drive physical design and timing of high-frequency DPUs/SoCs, optimizing constraints and synthesis parameters to hit performance, power, and area targets. You’ll handle RTL-to-GDS2 flows, ECOs, floorplanning, and timing convergence, leveraging STA, LEC, and industry EDA tools (PrimeTime/Tempus). Strong Python/Tcl/Make automation and a background in Synthesis & Timing are required.
Location: Durham
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, chiplet level, and/or full chip level.
  • •Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets.
  • •Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
  • •Collaborate with design teams to ensure timing closure across sub-blocks and full-chip level.
  • •Contribute to methodology and/or flow development as well as automation to streamline timing convergence.

Pay and Benefits

Salary: USD 168,000 - 264,500 annually
Equity and Bonus:Equity
Perks:Equity

Key Requirements

  • •BS in Electrical or Computer Engineering with 8 years experience or MS with 4+ years experience in Synthesis and Timing
  • •Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence
  • •Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
  • •Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, with ECO implementation experience
  • •Background in logic synthesis and/or logical equivalence checking (LEC)
Experience:8+ yearsSemiconductorHardwareASICOn-chip design
Education:Bachelor's in Electrical or Computer EngineeringN/A
Skills:TeamworkCommunicationProblem-solving
Tech Stack:PythonTclMakeSynopsys PrimeTimeCadence TempusEDA tools

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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