Senior Mask Design Engineer - Hardware

Design and verify mixed-signal chiplet interface layouts for state-of-the-art sub-micron CMOS processes. Use Cadence tools (especially Virtuoso) to perform physical layout, floorplanning, and rule/schematic verification. Collaborate with mixed-signal design engineers to customize VLSI integrations, ensuring high-quality layout execution in fast-paced projects. Contribute scripting and DRC/LVS flow customization expertise for efficient iteration.