FPGA Design Engineer (Timing)
AMD
San Jose
Workplace: HybridFull timeUSD 124,040 - 212,640 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Analytical skills","Problem-solving","Teamwork","Willing to learn"]Develop timing models for the full FPGA so the FPGA toolset can ensure proper timing for user-created designs. You’ll run simulations on FPGA component sections, derive and validate timing numbers, and ensure results aren’t caused by simulation setup issues. Work with custom FPGA designs and silicon testing to correlate simulated and measured timing. Automate timing capture and analysis with Perl and Python scripts.

