SpaceX

1 month ago

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Senior hardware verification engineer responsible for full-chip DRC/LVS/ESD/PERC signoff and developing robust physical verification flows for advanced SoCs used in SpaceX Starlink, collaborating with foundry teams and ASIC teams to ensure tapeout readiness and high-quality silicon.

Location: Irvine, Austin, Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
•Develop, maintain, and optimize physical verification flows for advanced node SoC’s
•Interpret and implement foundry DRM — translate rule updates into verified flow changes
•Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
•Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
•Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams

Pay and Benefits

Perks:Health Insurance401kPaid LeaveDisability Insurance

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering or computer science
•5+ years of ASIC and/or physical design flow development experience in industry
•Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
•Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
•Direct foundry DRM experience — able to read, interpret, and implement complex rule decks

Experience:5+ yearsSemiconductorASICHardware verification

Education:Bachelor's

Skills:Self-motivatedProblem-solvingTeamworkCommunication

Languages:English

Tech Stack:CalibreICVPegasusPythonPerlC shellTCLBashMakefile

Company Brief

SpaceX

Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn

Loading job details...

Preparing the role view and application actions.

SpaceX

1 month ago

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Location: Irvine, Austin, Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
•Develop, maintain, and optimize physical verification flows for advanced node SoC’s
•Interpret and implement foundry DRM — translate rule updates into verified flow changes
•Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
•Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
•Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams

Pay and Benefits

Perks:Health Insurance401kPaid LeaveDisability Insurance

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering or computer science
•5+ years of ASIC and/or physical design flow development experience in industry
•Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
•Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
•Direct foundry DRM experience — able to read, interpret, and implement complex rule decks

Experience:5+ yearsSemiconductorASICHardware verification

Education:Bachelor's

Skills:Self-motivatedProblem-solvingTeamworkCommunication

Languages:English

Tech Stack:CalibreICVPegasusPythonPerlC shellTCLBashMakefile

Company Brief

SpaceX

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn