IP RTL Design Engineer
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 6-15 yearsEducation: bachelorsSkills: ["Verilog","VHDL","AXI","AXI-Lite","APB","IOSF-SB","HBW","LBW","RTL","Timing analysis","Formal verification","Debugging RTL"]Component IP RTL Design Engineer for Intel Unified Chassis focusing on protocol bridges. Develop, implement, and verify IP blocks (AXI/AXI-Lite/APB/IOSF-SB/HBW/LBW), collaborate with architects to define microarchitecture, and ensure secure, diagnosable IP delivery through RTL design, simulation, and verification across SoC environments.
