Senior ASIC DFT Engineer

Intel
Israel
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Ownership","Cross-functional collaboration","Rigorous thinking","Technical decision-making"]

Own central DFT architecture and strategy for complex AI acceleration IPs and subsystems, balancing test coverage with area, timing, and power. Build and drive DFT implementation (scan, compression, boundary scan/JTAG, MBIST, test access/control) to achieve fault coverage closure. Lead ATPG and pattern generation, improve DFT methodologies and workflows, and advance adoption of AI tools across the DFT flow while partnering with design, verification, physical design, and product/test teams for bring-up and yield/debug.

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FursaFursa
Intel
Intel
1 day ago

Senior ASIC DFT Engineer

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Job Summary

Own central DFT architecture and strategy for complex AI acceleration IPs and subsystems, balancing test coverage with area, timing, and power. Build and drive DFT implementation (scan, compression, boundary scan/JTAG, MBIST, test access/control) to achieve fault coverage closure. Lead ATPG and pattern generation, improve DFT methodologies and workflows, and advance adoption of AI tools across the DFT flow while partnering with design, verification, physical design, and product/test teams for bring-up and yield/debug.
Location: Israel
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Define DFT architecture and strategy for complex AI acceleration IPs and subsystems, balancing test coverage, area, timing, and power.
  • •Build DFT implementation (scan, compression, boundary scan/JTAG, MBIST, test access/control) and drive fault coverage closure to sign-off.
  • •Lead ATPG and pattern generation.
  • •Develop DFT methodologies and workflows and help drive best practices across the team.
  • •Collaborate with design, verification, physical design, and product/test engineering for silicon bring-up, debug, and yield/quality analysis.

Pay and Benefits

Perks:Hybrid Work

Key Requirements

  • •B.Sc. in Electrical Engineering, Computer Engineering, or equivalent.
  • •6+ years of hands-on DFT experience driving DFT solutions from architecture through silicon bring-up.
  • •Strong command of DFT techniques including scan insertion, compression, ATPG, boundary scan (JTAG), and MBIST.
  • •Demonstrated ownership of complex DFT solutions and ability to drive technical decisions across cross-functional teams.
  • •Strong interest in using AI tools to advance the DFT flow.
Experience:AI hardwareAI/ML accelerators
Education:Bachelor's
Skills:OwnershipCross-functional collaborationRigorous thinkingTechnical decision-making
Tech Stack:DFTScan insertionCompressionATPGBoundary scanJTAGMBISTFault coverage closureAI toolsAI/ML accelerator designsHierarchical DFTLow-power testIn-system testSilicon debugYield analysis

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
Glassdoor
Glassdoor: 3.8
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