Hardware - Silicon Validation Engineer (NPU SoC)

FuriosaAI
Seoul
Workplace: OnsiteFull timeFunction: Healthcare (Clinical, Medical, Wellness)Skills: ["Problem-solving","Debugging","Issue investigation","Coverage management"]

Lead system-level validation for NPU SoC tape-out to commercialization, ensuring full functionality between RTL/DV and firmware/OS. Drive 1st silicon bring-up across key compute and interconnect blocks (CPU subsystem, NoC, memory LPDDR/HBM, high-speed I/F, board booting). Build and execute validation plans from pre-silicon (emulation/FPGA) to post-silicon, write bare-metal test firmware, and troubleshoot HW/SW boundary issues using JTAG/Trace32. Support performance optimization and test automation with CI/CD integration.

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FursaFursa
FuriosaAI
FuriosaAI
1 week ago

Hardware - Silicon Validation Engineer (NPU SoC)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 12 minutes agoStatus: Live

Job Summary

Lead system-level validation for NPU SoC tape-out to commercialization, ensuring full functionality between RTL/DV and firmware/OS. Drive 1st silicon bring-up across key compute and interconnect blocks (CPU subsystem, NoC, memory LPDDR/HBM, high-speed I/F, board booting). Build and execute validation plans from pre-silicon (emulation/FPGA) to post-silicon, write bare-metal test firmware, and troubleshoot HW/SW boundary issues using JTAG/Trace32. Support performance optimization and test automation with CI/CD integration.
Location: Seoul
Workplace: Onsite
Employment Type: Full time
Job Function: Healthcare (Clinical, Medical, Wellness)

Key Responsibilities

  • •Lead NPU 1st silicon bring-up by validating core compute, CPU subsystem, NoC, memory subsystem (LPDDR/HBM), and high-speed interfaces, including board bring-up and booting/clock-reset initialization.
  • •Establish and run validation methodology by creating test plans and coverage management across pre-silicon (emulator/FPGA) and post-silicon environments.
  • •Develop and write test firmware (bare-metal) and create scenarios for validating each IP.
  • •Perform system-level issue debugging and derive workarounds for complex HW/SW boundary problems, using JTAG and Trace32 and reporting to related teams.
  • •Support performance validation and optimization for NPU data pipeline and memory bandwidth, and improve validation efficiency via test automation with CI/CD-connected validation environments.

Key Requirements

  • •Experience with SoC/ASIC or complex Silicon/System Validation, with senior/lead-level experience required for lead candidates.
  • •Strong understanding of ARM architecture and AMBA bus (AXI, AHB) plus overall SoC/computer architecture.
  • •Programming ability for embedded IP testing and hardware control using Embedded C/C++ and Rust in bare-metal environments.
  • •Hands-on validation methodology experience covering test plan creation, bug tracking, and coverage.
  • •Debugging expertise with JTAG debuggers (e.g., Trace32) and strong HW/SW co-debugging skills.
Skills:Problem-solvingDebuggingIssue investigationCoverage management
Tech Stack:ARM ArchitectureAMBA AXIAMBA AHBRTLDVEmbedded CEmbedded C++RustBare-metalEmulatorFPGAPalladiumZebuLPDDRHBMEthernetCXLNoCJTAGTrace32

Company Brief

FuriosaAI
Designs and develops data‑center AI inference accelerators (RNGD) and a full stack hardware‑software platform to deliver energy‑efficient, high‑performance AI compute for enterprise and cloud customers.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Scaleup
Valuation: USD 500M to 1B
Funding: Series C
Headquarters: Seoul, South Korea
Founded: 2017
Glassdoor
Glassdoor: 4.6
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