Engineer/ Sr Memory Layout Engineer-DPG-LPDDR

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringEducation: mastersSkills: ["Ownership","Independent planning","Execution","Quality focus","Reliability focus"]

Develop and deliver memory layout blocks for DRAM/LPDDR products, working on bit cell layout creation and pitch matching. You will design row/column decoder (XDEC/YDEC) layouts, understand memory array hierarchy and decode paths, and implement high-quality custom layouts using Cadence Virtuoso. Validate with Calibre DRC/LVS, debug and close issues, and apply device physics expertise to improve reliability, power, and schedule.

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FursaFursa
Micron Technology
Micron Technology
2 weeks ago

Engineer/ Sr Memory Layout Engineer-DPG-LPDDR

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Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Develop and deliver memory layout blocks for DRAM/LPDDR products, working on bit cell layout creation and pitch matching. You will design row/column decoder (XDEC/YDEC) layouts, understand memory array hierarchy and decode paths, and implement high-quality custom layouts using Cadence Virtuoso. Validate with Calibre DRC/LVS, debug and close issues, and apply device physics expertise to improve reliability, power, and schedule.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Create bit cell layout and perform pitch matching for memory designs.
  • •Develop row decoder (XDEC) and column decoder (YDEC) layout components.
  • •Implement custom layout blocks in Cadence Virtuoso and apply transistor matching strategies.
  • •Run and debug Calibre DRC/LVS to ensure layout correctness and closure.
  • •Plan and deliver memory layout blocks with a strong focus on quality, power, schedule, and reliability.

Key Requirements

  • •2+ years of proven experience in memory and full-custom layout development.
  • •Strong hands-on experience with bit cell layout creation and pitch matching.
  • •Strong exposure to row decoder (XDEC) and column decoder (YDEC) layout development.
  • •Proficiency with Cadence Virtuoso for custom layout implementation and solid experience with Calibre DRC/LVS debug and closure.
  • •Strong understanding of DRAM/LPDDR memory architecture, array organization, and peripheral integration.
Experience:MemoryFull-custom layoutDRAMLPDDRCustom layoutSemiconductorAI/ML
Education:Master's in Electronics, Electronics & Communications, Microelectronics, or VLSI
Skills:OwnershipIndependent planningExecutionQuality focusReliability focus
Tech Stack:Cadence VirtuosoCalibre DRCCalibre LVSAI/MLArtificial IntelligenceEM/ESD

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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