Design Verification Engineer

Broadcom
San Jose
Workplace: OnsiteFull timeUSD 120,000 - 192,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Communication"]

Verify cutting-edge networking ASIC designs for Broadcom’s Tomahawk platform, covering L2/L3 switching and routing features. Build SystemVerilog/UVM verification environments, including testbenches, verification APIs, and automation scripts to run across toolchains. Develop detailed test plans, implement executable test suites, and drive pre-silicon verification to completion using functional and code coverage metrics, from plan definition to coverage closure.

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FursaFursa
Broadcom
Broadcom
3 months ago

Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 21 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Verify cutting-edge networking ASIC designs for Broadcom’s Tomahawk platform, covering L2/L3 switching and routing features. Build SystemVerilog/UVM verification environments, including testbenches, verification APIs, and automation scripts to run across toolchains. Develop detailed test plans, implement executable test suites, and drive pre-silicon verification to completion using functional and code coverage metrics, from plan definition to coverage closure.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Participate in verification of L2/L3 network switching and routing ASICs and their subsystems.
  • •Understand chip architecture and create in-depth test plans for key networking features including traffic streaming, traffic management, scheduling/shaping, and latency/performance characterization.
  • •Develop verification environments, including testbenches and verification APIs, plus scripts and Makefiles to support execution across toolchains.
  • •Implement test plans as executable test suites using a SystemVerilog verification environment.
  • •Execute pre-silicon verification to completion using functional and code coverage metrics to measure progress.

Pay and Benefits

Salary: USD 120,000 - 192,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEsppPaid Leave

Key Requirements

  • •MSEE or BSEE (or equivalent) with concentration in digital design and strong academic standing; typically 8+ years with a BS, 6+ with an MS, or 3+ with a PhD (or equivalent).
  • •Familiarity with hardware description languages including Verilog/SystemVerilog/UVM.
  • •Experience with verification/validation techniques using modular, reusable object-oriented environments (e.g., SystemVerilog, Perl, Python).
  • •Strong end-to-end verification experience from test plan definition through coverage closure for ASIC/SOC designs that reached mass production.
  • •Excellent verbal and written communication skills.
Experience:8+ yearsASICSOCNetworkingSemiconductorsPre-silicon verification
Education:Bachelor's in digital design
Skills:Communication
Tech Stack:SystemVerilogVerilogUVMPerlPythonObject-oriented programmingTestbenchesVerification APIsMakefilesCode coverageFunctional coverageASICSoC

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn